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CY29940AI bảng dữ liệu(PDF) 3 Page - Cypress Semiconductor

tên linh kiện CY29940AI
Giải thích chi tiết về linh kiện  2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
PDF  7 Pages
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
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CY29940AI bảng dữ liệu(HTML) 3 Page - Cypress Semiconductor

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CY29940
Document #: 38-07283 Rev. *B
Page 3 of 7
Maximum Ratings[2]
Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature: ................................ –65
°C to + 150°C
Operating Temperature: ................................ –40
°C to +85°C
Maximum ESD Protection............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic volt-
age level (either VSS or VDD).
Notes:
2.
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3.
Inputs have pull-up/pull-down resistors that effect input current.
4.
The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification. Driving series or parallel terminated 50
Ω (or 50Ω to VDD/2) transmission lines
5.
Outputs driving 50
Ω transmission lines.
6.
See Figure 1 &2.
7.
50% input duty cycle.
DC Parameters: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit.
VIL
Input Low Voltage
VSS
0.8
V
VIH
Input High Voltage
2.0
VDD
V
IIL
Input Low Current[3]
–200
µA
IIH
Input High Current[3]
200
µA
VPP
Peak-to-Peak Input
Voltage
PECL_CLK
500
1000
mV
VCMR
Common Mode Range[4]
PECL_CLK
VDD = 3.3V
VDD – 1.4
VDD – 0.6
V
VDD = 2.5V
VDD – 1.0
VDD – 0.6
V
VOL
Output Low Voltage[5, 6, 7]
IOL = 20 mA
0.5
V
VOH
Output High Voltage[5, 6, 7]
IOH = –20 mA, VDDC = 3.3V
2.4
V
IOH = –20 mA, VDDC = 2.5V
1.8
V
IDDQ
Quiescent Supply
Current
57
mA
IDD
Dynamic Supply
Current
VDD = 3.3V, Outputs @
150 MHz, CL=15 pF
285
mA
VDD = 3.3V, Outputs @
200 MHz, CL=15 pF
335
VDD = 2.5V, Outputs @
150 MHz, CL=15 pF
200
VDD = 2.5V, Outputs @
200 MHz, CL=15 pF
240
Zout
Output Impedance
VDD = 3.3V
8
12
16
Ω
VDD = 2.5V
10
15
20
Cin
Input Capacitance
4
pF



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