SDA9488X datasheet(21/87 Pages) MICRONAS

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SDA 9488X

SDA 9588X

System Description

Micronas

4-21

Preliminary Data Sheet

Table 4-10

Required number of lines for frame mode display

The system may be forced to field mode by means of FIESEL. Either first or second field

is selectable. ’One of both’ takes every second field independent of the field number.

This is meant for sources generating only one field (e.g. video-games).

For progressive scan conversion systems and HDTV / (S)VGA displays a line doubling

mode is available (PROGEN). Every line of the inset picture is read twice.

Memory writing is stopped by FREEZE bit. The field stored in the memory is then

continuously read. As the picture decimation is done before storing, the picture size of a

frozen picture can not be changed.

Depending on the phase between inset and parent signals a correction of the display

raster for the read out data is performed. Synchronization of memory reading with the

parent channel is achieved by processing the parent horizontal and vertical

synchronization signals. Horizontal and vertical pulses may be provided. The signals are

fed to the IC at pin HSP for horizontal synchronization and pin VSP for vertical

synchronization. HSPINV or VSPINV respectively allow an inversion of the expected

signal polarity.

Figure 4-7

Field detection and phase adjustment of vertical pulse (VSP)

FMACTP

parent

standard

number of

lines per field

FMACTI

inset

standard

number of

lines per field

50 Hz

310...315

50 Hz

310...315

50 Hz

290...325

50 Hz

290...325

60 Hz

260...265

60 Hz

260...265

60 Hz

250...275

60 Hz

250...275

VSPDEL

max=151 (75) ←s

values in brackets () apply for 100Hz systems

field 0 window

field 1 window

tH = 64 (32)

←s

tH/2 = 32 (16)

←s

HSP

VSP

VSPD

(internal)

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