PLL1700ESLASH2K datasheet(3/15 Pages) TI1

3 / 15 page

PLL1700

SBOS096A

www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications at TA = +25°C, VDD = VDDP = +5V, VDDB = +3.3V, fM = 27MHz crystal oscillation, and fS = 48kHz, unless otherwise noted.

PLL1700E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUT/OUTPUT

Input Logic Level:

TTL-Compatible

VIH(1)

2.0

VDC

VIL(1)

0.8

VDC

VIH(2)

1.2

VDC

VIL(2)

0.4

VDC

Input Logic Current:

IIH(1)

VIN = VDD

200

µA

IIL(1)

VIN = 0V

–1

µA

IIH(2)

VIN = VDD

4mA

IIL(2)

VIN = 0V

–800

µA

Output Logic Level:

CMOS

VOH(3)

IOH = 4mA

VDDB – 0.4V

VDC

VOL(3)

IOL = 4mA

0.4

VDC

Sampling Frequency (fS)

Standard fS

44.1

kHz

Double fS

88.2

kHz

MASTER CLOCK (MCKO, MCKO)

fM = 27MHz, CL = 20pF

Master Clock Frequency

26.73

27.27

MHz

Clock Jitter(4)

300

Clock Duty Cycle

MCKO

C1 = C2 = 15pF

For Crystal Oscillation

MCKO

Clock Duty Cycle

MCKO

For External Clock

MCKO

PHASE LOCK LOOP (PLL)

fM = 27MHz, CL = 20pF

Generated System Clock Frequency

SCKO1

Fixed

33.8688

MHz

SCKO2

256fS

8.192

24.576

MHz

SCKO3

384fS

12.288

36.864

MHz

SCKO4

768fS

24.576

36.864

MHz

Generated Clock Rise Time(3)

20% to 80% VDDB

5ns

Generated Clock Fall Time(3)

80% to 20% VDDB

5ns

Generated Clock Duty Cycle

SCKO1, SCKO3, SCKO4

SCKO2 (standard)

SCKO2 (double)(5)

Generated Clock Jitter(4)

SCKO1, SCKO2 (standard), SCKO4

300

SCKO3

150

SCKO2 (double)

450

Settling Time

To Programmed Frequency

Power-Up Time

To Programmed Frequency

POWER SUPPLY REQUIREMENTS

Voltage Range

VDD, VDDP

+4.5

+5.5

VDC

VDDB

+2.7

+3.3

+3.6

VDC

Supply Current(6):

IDD + IDDP

VDD = VDDP = 5V, fS = 48kHz

IDDB

VDDB = +3.3V, fS = 48kHz

Power Dissipation

fS = 48kHz

110

TEMPERATURE RANGE

Operation

–25

+85

°C

Storage

–55

+125

°C

NOTES: (1) ML, MC, MD, MODE, RST (Schmitt-trigger input with internal pull-down resistor).

(2) XT1, when an external 27MHz clock is used, the buffer ICs, such as 74HC04, are recommended to interface to XT1.

(3) MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.

(4) Jitter performance is specified as standard deviation of jitter under 27MHz crystal oscillation.

(5) When SCKO2 is set to double rate clock output, its duty cycle is 33%.

(6) fM = 27MHz crystal oscillation, no load on MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.

PLL1700E/2K bảng dữ liệu(PDF) 3 Page - Texas Instruments

PLL1700E/2K bảng dữ liệu(HTML) 3 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

bảng dữ liệu tải về

Link URL