DS90CF583 Pin Descriptions — FPD Link Transmitter

Pin Name

I/O

No.

Description

TxIN

I

28

TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,

FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL)

TxOUT+

O

4

Positive LVDS differential data output

TxOUT−

O

4

Negative LVDS differential data output

FPSHIFT IN

I

1

TTL level clock input. The falling edge acts as data strobe

TxCLK OUT+

O

1

Positive LVDS differential clock output

TxCLK OUT−

O

1

Negative LVDS differential clock output

PWR DOWN

I

1

TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power

down

V

CC

I

4

Power supply pins for TTL inputs

DS012616-18

FIGURE 16. Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF583)

DS012616-21

FIGURE 17. Receiver Powerdown Delay

DS012616-22

FIGURE 18. Transmitter Powerdown Delay

www.national.com

10