GS2985 datasheet(28/45 Pages) SEMTECH

28 / 45 page

GS2985 Multi-Rate SDI Reclocker with Equalization &

De-emphasis

Data Sheet

36663 - 5

July 2012

28 of 45

Proprietary & Confidential

This is done by setting the RST bit low in the command word. This will guarantee the CSR

will not start up in a random state.

A simple way to issue the required reset of the CSR is to hold the slave device’s SDI input

LOW for an entire 64 cycle WRITE communication. Details of the WRITE operation are

found in section 4.15.6 below.

4.15.4 Clock & Data Timing

The SPI signals are Serial Data Input (SDI), Serial Data Output (SDO), Active Low Chip

Select (CS), and Serial Clock Input (SCK). The host interface operates in SPI Mode 0, i.e.

the SDI input will latch data in on the rising edge of SCK. The SDO data output will

transition on falling edges of SCK. Data is transmitted or received on the SPI port MSB

first LSB last.

Figure 4-4: Data Clock Alignment

4.15.5 Single Device Operation

For applications with a single device or applications with multiple devices where daisy

chaining is not desired, the chain position bits C[6:0] should always be set to 0. As a

by-product of the daisy chaining feature, Read and Write operations experience a 32

SCK cycle latency from SDI to SDO. For more details on daisy-chaining, refer to

Section 4.15.8 on page 32.

Figure 4-5: 16-bit Command Format

SCK

Cycle #

SDO

SDI

A[4:0]

RST

Read/

Write

Reset

Address

C N[6:0] = `0000000’

Chain Position

GS2985 bảng dữ liệu(PDF) 28 Page - Semtech Corporation