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SCL

A0

GND

Output

Buffer

Power-Down

Control Logic

Resistor

Network

Ref (+) Ref(−)

8-Bit

DAC

Control

Logic

DAC

Register

Power-On

Reset

SDA

PIN CONFIGURATIONS

A0

SCL

SDA

6

5

4

1

2

3

GND

1

2

3

6

5

4

(TOP VIEW)

(BOTTOM VIEW)

Lot Trace Code

DAC5571

SLAS405 – DECEMBER 2003

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE

SPECIFIED TEM-

PACKAGE

ORDERING NUM-

PRODUCT

PACKAGE

DESIG-

TRANSPORT MEDIA

PERATURE RANGE

MARKING

BER

NATOR

DAC5571IDBVT

250 Piece Small Tape and Reel

DAC5571

SOT23-6

DBV

-40

°C to +105°C

D571

DAC5571IDBVR

3000 Piece Tape and Reel

PIN DESCRIPTION (SOT23-6)

PIN

NAME

DESCRIPTION

1

Analog output voltage from DAC

Ground reference point for all

2

GND

circuitry

3

Analog Voltage Supply Input

4

SDA

Serial Data Input

5

SCL

Serial Clock Input

6

A0

Device Address Select

LOT

Year (3 = 2003); M onth (1–9 = JAN–SEP; A=OCT,

TRACE

B=NOV, C=DEC); LL– Random code generated

CODE:

when assembly is requested

2