NRND

TP3404

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SNOS703 – DECEMBER 2004

When the transmit direction (towards the line) is disabled there will be all “ONE's” (scrambled) as data for this

channel at the Lo pin. If the receive direction (from the line) is disabled, BO will stay high impedance for the

programmed time slot while, if it is enabled, data out on BO in the assigned time slot is the data from Li.

BITS 5–0: TS5–TS0

These bits define the binary number of the time-slot selected. Time-slots are numbered from 0–63. The frame

sync signal is used as marker pulses for the beginning of time slot 0.

Table 4. Byte 2 of Register TSXB1, TSXB2, TSRB1 or TSRB2 for B Channel Time-Slot Assignment

Bit Number and Name

Function

7

6

5

4

3

2

1

0

EB

X

TS5

TS4

TS3

TS2

TS1

TS0

0

X

X

X

X

X

X

X

Disable B1 and/or B2

1

X

Assign One Binary Coded Time-Slot from 0–63

Enable B1 and/or B2

REGISTERS TXD, TRD

The data format for all D channel time-slot assignment registers is as follows:

Data transparency between the digital interface and the line interface for the D channels can be controlled via the

Channel Control Register, see Table 3.

BITS 7–0: TS7–TS0

These bits define the binary number of the sub-slot selected. Sub-slots are numbered from 0–255. The frame

sync signal is used as marker pulses for the beginning of Sub-slot 0.

Table 5. Byte 2 of Register TSXD or TSRD for D Channel Time-Slot Assignment

Bit Number and Name

7

6

5

4

3

2

1

0

SS

SS

SS

SS

SS

SS

SS

SS

7

6

5

4

3

2

1

0

Assign One Binary Coded Sub-Slot from 0–255 for D Channel

Figure 5. QDASL Digital Interface Timing

Copyright © 2004, Texas Instruments Incorporated

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