A25GFO080QL datasheet(25/58 Pages) AMICC

25 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Program OTP (POTP)

The Program OTP instruction (POTP) is used to program at

most 64 bytes to the OTP memory area (by changing bits

from 1 to 0, only). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded,

the device sets the Write Enable Latch (WEL) bit.

The Program OTP instruction is entered by driving Chip

Select ( S ) Low, followed by the instruction code, three

address bytes and at least one data byte on Serial Data input

(DI).

Chip Select ( S ) must be driven High after the eighth bit of

the last data byte has been latched in, otherwise the

Program OTP instruction is not executed.

The instruction sequence is shown in Figure 14.

As soon as Chip Select ( S ) is driven High, the self-timed

Page Program cycle (whose duration is tPP) is initiated. While

the Program OTP cycle is in progress, the Status Register

may be read to check the value of the Write In Progress

(WIP) bit. The Write In Progress (WIP) bit is 1 during the

self-timed Program OTP cycle, and it is 0 when it is

completed. At some unspecified time before the cycle is

complete, the Write Enable Latch (WEL) bit is reset.

To lock the OTP memory:

Bit 0 of the OTP control byte, that is byte 63, (see Figure 14)

is used to permanently lock the OTP memory array.

• When bit 0 of byte 63 = ’1’, the OTP memory array can be

programmed.

• When bit 0 of byte 63 = ‘0’, the OTP memory array are

read-only and cannot be programmed anymore.

Once a bit of the OTP memory has been programmed to ‘0’,

it can no longer be set to ‘1’.

Therefore, as soon as bit 0 of address 63h (control byte) is

set to ‘0’, the 64 bytes of the OTP memory array become

read-only in a permanent way.

Any Program OTP (POTP) instruction issued while an Erase,

Program or Write Status Register cycle is in progress is

rejected without having any effect on the cycle that is in

progress.

Figure 14. Program OTP (POTP) instruction sequence

Instruction (42h)

MSB

810

0 1 234 5 6 7

24-Bit Address

28 29 30 31

23 22 21

3 21 0

40 41 42 43 44 45 46 47

65 4

48 49 50 51 52 53 54 55

Data Byte 2

MSB

7 6 54 32 1

MSB

7 6 54 32 1 0

32 33 34 35 36 37 38 39

Data Byte 1

65 04

21 00

MSB

Data Byte 3

Data Byte n

Note: A23 to A6 are don’t care. (1

≤ n ≤ 64)

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