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MSP430F67791A
, MSP430F67781A, MSP430F67771A, MSP430F67761A, MSP430F67751A
MSP430F67691A
, MSP430F67681A, MSP430F67671A, MSP430F67661A, MSP430F67651A
MSP430F67491A, MSP430F67481A, MSP430F67471A, MSP430F67461A, MSP430F67451A
SLAS983 – MAY 2014
www.ti.com
4.2
Signal Descriptions
Table 4-3 describes the signals for all devices in the PEU package. See Table 4-4 for the signals in the
PZ package.
Table 4-3. Terminal Functions – PEU Package
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
PEU
XIN
1
I/O
Input terminal for crystal oscillator
XOUT
2
I/O
Output terminal for crystal oscillator
AUXVCC3
3
Auxiliary power supply AUXVCC3 for backup subsystem
RTCCAP1
4
I
External time capture pin 1 for RTC_C
RTCCAP0
5
I
External time capture pin 0 for RTC_C
General-purpose digital I/O with port interrupt
SMCLK clock output
P1.5/SMCLK/CB0/A5
6
I/O
Comparator_B input CB0
Analog input A5 - 10-bit ADC
General-purpose digital I/O with port interrupt
MCLK clock output
P1.4/MCLK/CB1/A4
7
I/O
Comparator_B input CB1
Analog input A4 - 10-bit ADC
General-purpose digital I/O with port interrupt
P1.3/ADC10CLK/A3
8
I/O
ADC10_A clock output
Analog input A3 - 10-bit ADC
General-purpose digital I/O with port interrupt
P1.2/ACLK/A2
9
I/O
ACLK clock output
Analog input A2 - 10-bit ADC
General-purpose digital I/O with port interrupt
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
P1.1/TA2.1/VeREF+/A1
10
I/O
Positive terminal for the ADC's reference voltage for an external applied reference voltage
Analog input A1 - 10-bit ADC
General-purpose digital I/O with port interrupt
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
P1.0/TA1.1/VeREF-/A0
11
I/O
Negative terminal for the ADC's reference voltage for an external applied reference voltage
Analog input A0 - 10-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P2.4/PM_TA2.0
12
I/O
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt and mappable secondary function
P2.5/PM_UCB0SOMI/
13
I/O
Default mapping: eUSCI_B0 SPI slave out master in
PM_UCB0SCL
Default mapping: eUSCI_B0 I2C clock
(1)
I = input, O = output
10
Terminal Configuration and Functions
Copyright © 2014, Texas Instruments Incorporated
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Product Folder Links: MSP430F67791A MSP430F67781A MSP430F67771A MSP430F67761A MSP430F67751A
MSP430F67691A MSP430F67681A MSP430F67671A MSP430F67661A MSP430F67651A MSP430F67491A
MSP430F67481A MSP430F67471A MSP430F67461A MSP430F67451A



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