TNETV2840ENGGU datasheet(43/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

3.2.4 Hardware Timer

Each 5441 subsystem has one independent software programmable timer. The memory-mapped registers

control the operation of the timer. The timer resolution is the clock rate of the CPU. The timer output shares

the pin with GPIO3 and is controlled by GPIO register bit 15.

The timer supports a 32-bit dynamic range. The timer consists of a programmable 16-bit main counter and

a programmable prescalar. The main counter is driven by the prescalar, which decrements by one at every

CPU clock. Once the prescalar reaches zero, the 16-bit counter decrements by one. When the 16-bit counter

decrements to zero, a maskable interrupt (TINT) is generated and the timer output pin (TOUT) asserts an

active-high pulse (2H − 2 ns, H = 0.5 clock cycle). The timer output pulse is driven on GPIO3 when the TOUT

bit is set to high in the GPIO register. When the timer is configured in continuous mode, the timer counter and

prescalar will be reloaded accordingly after the timer counter exhausts. The timer can be stopped, restarted,

reset, or disabled via the bits of the timer control register.

There are four 16-bit registers associated with the timer.

•

Timer counter register (TIM)

•

Timer period register (PRD)

•

Timer control register (TCR)

•

Timer second control register (TSCR)

3.2.4.1

TIM Register

This register is loaded with the period register (PRD) value and decrements once the PRD value is loaded.

3.2.4.2

PRD Register

This register is used to reload the timer counter register (TIM).

3.2.4.3

TCR Register

This register provides the control and status information. TCR bit fields are shown in Figure 3−21 and

described in Table 3−10.

43210

Reserved

SOFT

FREE

PSC

TRB

TSS

TDDR

R/W+0

LEGEND: R = Read, W = Write, +0 = Value at reset

Figure 3−21. Timer Control Register (TCR)

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