TMS570LS0232PZ datasheet(91/109 Pages) TI1

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TMS570LS0232

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SPNS242A – OCTOBER 2014 – REVISED JUNE 2015

Table 7-16. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =

input, and SPISOMI = output)(1)(2)(3)(4)

NO.

PARAMETER

MIN

MAX

UNIT

tc(SPC)S

Cycle time, SPICLK(5)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

2(6)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0)

3(6)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1)

td(SOMI-SPCL)S

Dealy time, SPISOMI data valid after SPICLK low (clock

trf(SOMI) + 20

polarity = 0)

4(6)

td(SOMI-SPCH)S

Delay time, SPISOMI data valid after SPICLK high (clock

trf(SOMI) + 20

polarity = 1)

Hold time, SPISOMI data valid after SPICLK high (clock

th(SPCL-SOMI)S

polarity =0)

5(6)

Hold time, SPISOMI data valid after SPICLK low (clock polarity

th(SPCH-SOMI)S

=1)

tsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock polarity = 0)

6(6)

tsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock polarity = 1)

High time, SPISIMO data valid after SPICLK high (clock

tv(SPCH-SIMO)S

polarity = 0)

7(6)

High time, SPISIMO data valid after SPICLK low (clock polarity

tv(SPCL-SIMO)S

= 1)

Delay time, SPIENAn high after last SPICLK high (clock

td(SPCH-SENAH)S

1.5tc(VCLK)

2.5tc(VCLK)+tr(ENAn) + 22

polarity = 0)

Delay time, SPIENAn high after last SPICLK low (clock polarity

td(SPCL-SENAH)S

1.5tc(VCLK)

2.5tc(VCLK)+tr(ENAn) + 22

= 1)

Delay time, SPIENAn low after SPICSn low (if new data has

td(SCSL-SENAL)S

tf(ENAn)

tc(VCLK)+tf(ENAn)+ 27

been written to the SPI buffer)

Delay time, SOMI valid after SPICSn low (if new data has been

td(SCSL-SOMI)S

tc(VCLK)

2tc(VCLK)+trf(SOMI)+ 28

written to the SPI buffer)

(1)

The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2)

If the SPI is in slave mode, the following must be true: tc(SPC)S

≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3)

For rise and fall timings, see Table 5-6.

(4)

tc(VCLK) = interface clock cycle time = 1 /f(VCLK)

(5)

When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.

(6)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Peripheral Information and Electrical Specifications

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