TMS320VC5504 datasheet(21/123 Pages) TI1

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TMS320VC5504

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SPRS609B – JUNE 2009 – REVISED JANUARY 2010

Table 3-9. Inter-Integrated Circuit (I2C) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

I2C

This pin is the I2C clock output. Per the I2C standard, an external pullup is required

SCL

I/O/Z

DVDDIO

on this pin.

This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup

SDA

I/O/Z

DVDDIO

is required on this pin.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

Table 3-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

Interface 0 (I2S0)

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_D0/

IPD

For I2S, it is I2S0 transmit data output I2S0_DX.

I2S0_DX/

I/O/Z

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[2]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_CLK/

IPD

For I2S, it is I2S0 clock input/output I2S0_CLK.

I2S0_CLK/

L10

I/O/Z

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[0]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_D1/

IPD

For I2S, it is I2S0 receive data input I2S0_RX.

I2S0_RX/

M10

I/O/Z

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[3]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC0, I2S0, and GPIO.

MMC0_CMD/

IPD

For I2S, it is I2S0 frame synchronization input/output I2S0_FS.

I2S0_FS/

M11

I/O/Z

DVDDIO

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

GP[1]

enabled or disabled via the PDINHIBR1 register.

Interface 1 (I2S1)

This pin is multiplexed between MMC1, I2S1 , and GPIO.

MMC1_D0/

IPD

For I2S, it is I2S1 transmit data output I2S1_DX.

I2S1_DX/

M14

I/O/Z

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[8]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC1, I2S1 , and GPIO.

MMC1_CLK/

IPD

For I2S, it is I2S1 clock input/output I2S1_CLK.

I2S1_CLK/

M13

I/O/Z

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[6]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between MMC1, I2S1 , and GPIO.

MMC1_D1/

IPD

For I2S, it is I2S1 receive data input I2S1_RX.

I2S1_RX/

M12

I/O/Z

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[9]

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed betweenn MMC1, I2S2 , and GPIO.

MMC1_CMD/

IPD

For I2S, it is I2S1 frame synchronization input/output I2S1_FS.

I2S1_FS/

L14

I/O/Z

DVDDIO

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

GP[7]

enabled or disabled via the PDINHIBR1 register.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1 , Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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