TMS320F241FN datasheet(13/122 Pages) TI1

13 / 122 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions - F243 PGE Package (Continued)

NAME

144

LQFP

TYPE†

RESET

STATE‡

DESCRIPTION

NAME

NO.

TYPE†

STATE‡

DESCRIPTION

TEST SIGNALS (CONTINUED)

TRST

JTAG test reset with internal pulldown. TRST, when driven high, gives

the scan system control of the operations of the device. If this signal is

not connected or driven low, the device operates in its functional mode,

and the test reset signals are ignored.

(

↓)

EMU0

I/O

Emulator I/O pin 0 with internal pullup. When TRST is driven high, this

pin is used as an interrupt to or from the emulator system and is defined

as input/output through the JTAG scan.

(

↑)

EMU1/OFF

I/O

Emulator I/O pin 1 with internal pullup. When TRST is driven high, this

pin is used as an interrupt to or from the emulator system and is defined

as input/output through JTAG scan.

(

↑)

SUPPLY SIGNALS

VSSO

−

Digital logic and buffer ground reference

VSSO

108

−

Digital logic and buffer ground reference

111

117

124

129

131

VDDO

−

Digital logic and buffer supply voltage

VDDO

−

Digital logic and buffer supply voltage

106

109

VDD

−

Digital logic supply voltage

VDD

125

−

Digital logic supply voltage

VSS

−

Digital logic ground reference

VSS

−

Digital logic ground reference

127

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS is enabled.

NOTE: Bold, italicized pin names indicate pin function after reset.

LEGEND:

↑ − Internal pullup

↓ − Internal pulldown

(Typical active pullup/pulldown value is 150

µA.)

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