3−2

The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block:

B[15:9]

Control address bits

B[8:0]

Control data bits

SCLK

SDI

ADDR

R/W ACK B15 − B8 ACK

B7 − B0

ACK

Start

Stop

1

78

9

1

89

18

9

Figure 3−2. 2-Wire Compatible Timing

3.1.3

Register Map

The TLV320DAC23 has the following set of registers, which are used to program the modes of operation.

ADDRESS

REGISTER

0000000

Left line input channel control

0000001

Right line input channel control

0000010

Left channel headphone volume control

0000011

Right channel headphone volume control

0000100

Analog audio path control

0000101

Digital audio path control

0000110

Power down control

0000111

Digital audio interface format

0001000

Sample rate control

0001001

Digital interface activation

0001111

Reset register

Left Line Input Channel Control (Address: 0000000)

BIT

D8

D7

D6

D5

D4

D3

D2

D1

D0

Function

LRS

LIM

X

X

X

X

X

X

X

Default

0

1

0

0

0

0

0

0

0

LRS

Left/right line simultaneous volume/mute update

Simultaneous update

0 = Disabled

1 = Enabled

LIM

Left line input mute

0 = Normal

1 = Muted

X

Reserved

Right Line Input Channel Control (Address: 0000001)

BIT

D8

D7

D6

D5

D4

D3

D2

D1

D0

Function

RLS

RIM

X

X

X

X

X

X

X

Default

0

1

0

0

0

0

0

0

0

RLS

Right/left line simultaneous volume/mute update

Simultaneous update

0 = Disabled

1 = Enabled

RIM

Right line input mute

0 = Normal

1 = Muted

X

Reserved