3−6

The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified

mode, which does not support 32 bits).

The digital audio interface consists of clock signal BCLK, data signals DIN and and the synchronization signal LRCIN.

BCLK is an output in master mode and an input in slave mode.

3.3.1.1 Right-Justified Mode

In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN (see

Figure 3-4).

LRCIN

BCLK

DIN

n

n−1

0

1

n−1

n

1/fs

Left Channel

Right Channel

1

0

0

MSB

LSB

Figure 3−4. Right Justified Mode Timing

3.3.1.2 Left-Justified Mode

In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN (see

Figure 3-5)

LRCIN

BCLK

DIN

n

n−1

0

1

n−1

n

1/fs

Left Channel

Right Channel

1

0

n

MSB

LSB

Figure 3−5. Left Justified Mode Timing

LRCIN

BCLK

DIN

n

n−1

0

1

n−1

n

1/fs

Left Channel

Right Channel

1

0

MSB

LSB

1BCLK