TLV320AIC21 datasheet(26/56 Pages) TI1

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Clock Source (MCLK, SCLK)

Serial Data Out (DOUT)

Serial Data In (DIN)

Frame-Sync FS

TLV320AIC20, TLV320AIC21

TLV320AIC24, TLV320AIC25

TLV320AIC20K, TLV320AIC24K

SLAS363D – MARCH 2002 – REVISED APRIL 2005

Functional Description (continued)

of time slots per frame sync (FS) to match the number of codecs in the serial interface so that no time slot is

wasted. Both the programming mode and the continuous data transfer mode of the TLV320AIC2x are compatible

with the TLV320AIC12. The TLV320AIC2x provides primary/secondary communication and continuous data

transfer with improvements and eliminates the requirements for hardware and software requests for secondary

communication as seen in the TLV320AIC10. The TLV320AIC2x continuous data transfer mode now supports

both master/slave stand-alone and cascade.

Table 1. Serial Interface Configurations

M/S PIN

FSD PIN

TLV320AIC2x CONNECTIONS

COMMENTS

MASTER

SLAVE

MASTER

SLAVE

Stand-alone

High

Low

Pull high

Low

Connect to the next slave's FS

Master-slave cascade

High

Low

Last slave's FSD pin is pulled high

(see Figure 23)

Slave-slave cascade

Not supported

MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughout

the device. SCLK is the bit clock used to receive and transmit data synchronously. When the device is in the

master mode, SCLK and FS are output and derived from MCLK in order to provide clocking the serial

communications between the device and a digital signal processor (DSP). When in the slave mode, SCLK and

FS are inputs. SCLK is controlled by TURBO bit (D7) in control register 2. In the standard operation (non-turbo,

TURBO = 0), SCLK frequency is defined by:

•

SCLK = (16 × FS × #Devices × mode)

Where:

•

FS is the frame-sync frequency. #Device is the number of the codec channels in cascade. (#Device = 2 for

stand-alone AIC2x) Mode is equal to 1 for continuous data transfer mode and 2 for programming mode.

DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the data

word is the ADC conversion result. In the control frame, the data is the register read results when requested by

the read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are all

zeroes. Valid data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). The

first bit transmitted on the falling edge of FS is the MSB of valid data.

The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of first

SCLK after FS. In a data frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit data

format is used, the LSB (D0) of every DAC channel is set to 1 to switch from the continuous data transfer mode

to the programming mode. In a control frame, the data is the control and configuration data that sets the device

for a particular function as described in Section 3.9, Control Register Programming.

The frame-sync signal (FS) indicates the device is ready to send and receive data. FS is an output if the M/S pin

is connected to HI (master mode) and an input if the M/S pin is connected to LO (slave mode).

Data is valid on the falling edge of the FS signal.

The frequency of FS is defined as the sampling rate of the TLV320AIC2x and derived from the master clock

MCLK as followed (see Section 3.1 Operating Frequencies for details):

•

FS = MCLK / (16 × P × N × M)

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