+ 1

2.2 PF

SHDN

GND

IN

OUT

FAULT

100

k

Ÿ

2.2 PF

CERAMIC

CC

33 nF

LP3982

www.ti.com

SNVS185E – FEBRUARY 2002 – REVISED OCTOBER 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP3982 can provide 300-mA output current with 2.5-V to 6-V input. It is stable with a 2.2-

μF ceramic output

capacitor. An optional external bypass capacitor reduces the output noise without slowing down the load

transient response. Typical output noise is 37

60 dB at 1 kHz.

8.2 Typical Application

8.2.1 Design Requirements

For typical ultra low-dropout CMOS-regulator applications, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Minimum input voltage

Nominal output voltage

3.3 V

Maximum output current

300 mA

RMS noise, 10 Hz to 100 kHz

PSRR at 1 kHz

60 dB

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Setting (ADJ Version Only)

The output voltage is set according to the amount of negative feedback (the pass transistor inverts the feedback

signal.) Figure 15 simplifies the topology of the LP3982. This type of regulator can be represented as an op amp

of this op amp is its extra-large output transistor that only sources current. In terms of its non-inverting

(5)

Utilize Equation 6 for adjusting the output to a particular voltage:

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