LP3954TLSLASHNOPB datasheet(33/60 Pages) TI1

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SCK

Data

BIT 1

LSB IN

LSB OUT

BIT 1

MSB OUT

BIT 7

BIT 8

BIT 9

BIT 14

MSB IN

R/W

Address

SCK

Don't Care

R/W

SCK

R/W

LP3954

www.ti.com

SNVS340D – JUNE 2005 – REVISED MARCH 2013

SPI INTERFACE

LP3954 is compatible with SPI serial bus specification and it operates as a slave. The transmission consists of

16-bit Write and Read Cycles. One cycle consists of 7 Address bits, 1 Read/Write (RW) bit and 8 Data bits. RW

bit high state defines a Write Cycle and low defines a Read Cycle. SO output is normally in high-impedance state

and it is active only when Data is sent out during a Read Cycle. A pull-up resistor may be needed in SO line if a

floating logic signal can cause unintended current consumption in the input circuits where SO is connected.The

Address and Data are transmitted MSB first. The Slave Select signal SS must be low during the Cycle

transmission. SS resets the interface when high and it has to be taken high between successive Cycles. Data is

clocked in on the rising edge of the SCK clock signal, while data is clocked out on the falling edge of SCK.

Figure 35. SPI Write Cycle

Figure 36. SPI Read Cycle

Figure 37. SPI Timing Diagram

SPI Timing Parameters

VDD = VDD_IO = 2.775V

Limit(1)

Symbol

Parameter

Unit

Min

Max

Cycle Time

Enable Lead Time

(1)

Note: Data ensured by design.

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