TLC2933

HIGHPERFORMANCE PHASELOCKED LOOP

SLAS136B − APRIL 1996 − REVISED JANUARY 2002

3

POST OFFICE BOX 655303

VCO inhibit function

The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO

INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during

the power-down mode as shown in Table 1.

Table 1. VCO Inhibit Function

VCO INHIBIT

VCO OSCILLATOR

VCO OUT

IDD(VCO)

Low

Active

Active

Normal

High

Stopped

Low level

Power Down

PFD operation

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase

difference between two frequency inputs supplied to FIN−A and FIN−B as shown in Figure 2. Nominally the

reference is supplied to FIN−A, and the frequency from the external counter output is fed to FIN−B. For clock

recovery PLL systems, other types of phase detectors should be used.

FIN− A

FIN− B

PFD OUT

VOH

Hi-Z

VOL

Figure 2. PFD Function Timing Chart

PFD inhibit control

A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops

phase detection as shown in Table 2. A high level on the PFD INHIBIT terminal can also be used as the

power-down mode for the PFD.

Table 2. VCO Output Control Function

PFD INHIBIT

DETECTION

PFD OUT

IDD(PFD)

Low

Active

Active

Normal

High

Stopped

Hi-Z

Power Down