WM8746

Advance Information

PP Rev 1.4 November 2001

19

DAC OUTPUT ATTENUATION

Register bits [7:0] of L0A and R0A control the left and right channel attenuation of DAC 0. Register

bits [7:0] of L1A and R1A control the left and right channel attenuation of DAC 1. Register bits [7:0] of

L2A and R2B control the left and right channel attenuation of DAC 2. Register bits [7:0] of MASTA

are a register that can be used to control attenuation of all channels.

Table 8 shows how the attenuation levels are selected from the 8-bit words.

XA[7:0]

ATTENUATION LEVEL

00(hex)

-

∞dB (mute)

01(hex)

-127.5dB

::

::

::

FE(hex)

-0.5dB

FF(hex)

0dB

Table 8 Attenuation Control Levels

EXTENDED INTERFACE CONTROL

It is possible to run the WM8746 channels at different rates with the front two channels running at

twice the rate of the rear four channels. In this mode which is enabled by bit 0 of register 9, the

interface runs at the faster data rate but pin 10 (LRCIN2) acts as the framing LRCIN for the rear

channels see Figure 9.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001001

Split rate mode

0

2SPD

0

Activates the split rate mode

0: Normal operation

1: Split rate operation

When the WM8746 receives updates to the volume levels it will, by default, wait for the signal to pass

on the output when the volume is changed. This function applies individually to each channel.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001001

Zero crossing detect

1

ZCD

0

Controls the ZCD

0: Enabled

1: Disabled