TFP201, TFP201A

TI PanelBus DIGITAL RECEIVER

SLDS116A - MARCH 2000 − REVISED JUNE 2000

14

POST OFFICE BOX 655303

TFP201/201A output driver configurations (continued)

Drive Strength (ST = high for high drive strength, ST=low for low drive strength.) The TFP201/201A allows

for selectable output drive strength on the data, control and ODCK outputs. See the dc specifications table for

times the drive as the low output drive strength.

Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high).

Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous

current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount

of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even

pixel is delayed from the latching edge of ODCK by 0.25 Tcip. (Tcip is the period of ODCK. The ODCK period

is 2Tpix when in 2-pixel/clock mode.)

Depending on system constraints of output load, pixel rate, panel input architecture and board cost the

TFP201/201A drive strength and staggered pixel options allow flexibility to reduce system power-supply noise,

ground bounce and EMI.

Power Management. The TFP201/201A offers several system power management features.

The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode,

all output drivers except SCDT and CTL1 are driven to a high impedance state while the rest of the device

circuitry remains active

The TFP201/201A power down (PD = low) is a complete power down in that it powers down the digital core,

the analog circuitry, and output drivers. All output drivers are placed into a Hi-z state. All inputs are disabled

except for the PD input. The TFP201/201A will not respond to any digital or analog inputs until PD is pulled high.

Both PDO and PD have internal pullups so if left unconnected they will default the TFP201/201A to normal

operating modes.

Sync Detect. The TFP201/201A offers an output, SCDT to indicate link activity. The TFP201/201A monitors

activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition

on DE, the TFP201/201A considers the link inactive and SCDT is driven low. While SCDT is low, if two DE

transitions are detected within 1600 pixel clock periods, the link will be considered active and SCDT is pulled

high.

SCDT can be used to signal a system power management circuit to initiate a system power down when the link

is considered inactive. The SCDT can also be tied directly to the TFP201/201A PDO input to power down the

output drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once

in complete power-down, the analog inputs are ignored and the SCDT state will not change. An external system

power management circuit to drive PD is preferred.

TI PowerPAD

 100-TQFP package

The TFP201/201A is packaged in TI’s thermally enhanced PowerPAD

 100TQFP packaging. The PowerPAD

package is a 14 mm

× 14 mm × 1 mm TQFP outline with 0.5mm lead-pitch. The PowerPAD package has a

specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the

same outline. The TI 100-TQFP PowerPAD

 package offers a back-side solder plane that connects directly

to the die mount pad for enhanced thermal conduction. Soldering the back side of the TFP201/201A to the

application board is not required thermally as the device power dissipation is well within the package capability

when not soldered.

Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations.

Since the die pad is electrically connected to the chip substrate and hence chip ground, connection of the

PowerPAD back side to a PCB ground plane will help to improve EMI, ground bounce, and power supply noise

performance.

Not Recommended for New Designs