24AA1025/24LC1025/24FC1025

DS20001941L-page 4

 2005-2013 Microchip Technology Inc.

FIGURE 1-1:

BUS TIMING DATA

11

WP setup time

4000

4000

600

600

600

—

—

—

—

—

ns

1.7V

2.5V

2.5V

1.8V

2.5V

12

WP hold time

4700

4700

1300

1300

1300

—

—

—

—

—

ns

1.7V

2.5V

2.5V

1.8V

2.5V

13

Output valid from clock

(Note 2)

—

—

—

—

—

3500

3500

900

900

400

ns

1.7V

2.5V

2.5V

1.8V

2.5V

14

Bus free time: Time the bus

must be free before a new

transmission can start

4700

4700

1300

1300

500

—

—

—

—

—

ns

1.7V

2.5V

2.5V

1.8V

2.5V

15

Input filter spike suppression

(SDA and SCL pins)

—

50

ns

All except 24FC1025 (Note 1 and Note 3)

16

Write cycle time (byte or page)

—

5

ms

—

17

Endurance

1,000,000

—

AC CHARACTERISTICS (Continued)

Industrial (I):

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Conditions

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,

please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

(unprotected)

(protected)

SCL

SDA

IN

SDA

OUT

WP

5

7

6

15

3

2

89

13

D3

4

10

11

12

14