LM93 datasheet(49/95 Pages) TI1

49 / 95 page

LM93

www.ti.com

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

Sleep

Bit

Name

R/W

Description

Masking

AD12_ERR

RWC

This bit is set when the AD_IN12 voltage has fallen outside the range defined by

S3*, S4/5*

the AD_IN12 Low Limit and the AD_IN12 High Limit registers.

AD13_ERR

RWC

This bit is set when the AD_IN13 voltage has fallen outside the range defined by

S3*, S4/5*

the AD_IN13 Low Limit and the AD_IN13 High Limit registers.

AD14_ERR

RWC

This bit is set when the AD_IN14 voltage has fallen outside the range defined by

S3*, S4/5*

the AD_IN14 Low Limit and the AD_IN14 High Limit registers.

AD15_ERR

RWC

This bit is set when the AD_IN15 voltage has fallen outside the range defined by

S3, S4/5

the AD_IN15 Low Limit and the AD_IN15 High Limit registers.

AD16_ERR

RWC

This bit is set when the AD_IN16 voltage has fallen outside the range defined by

none

the AD_IN16 Low Limit and the AD_IN16 High Limit registers.

3.17.4.4 Register 43h

B_Error Status 4

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

B_Error

D2_

D1_

DVDDP2

DVDDP1

SCSI2

SCSI1

43h

RWC

RES

00h

Status 4

ERR

_ERR

Sleep

Bit

Name

R/W

Description

Masking

1:0

RES

Reserved

N/A

SCSI1_ERR

RWC

SCSI Fuse Error

S3, S4/5

This bit is set if SCSI_TERM1 has been asserted.

SCSI2_ERR

RWC

SCSI Fuse Error

S3, S4/5

This bit is set if SCSI_TERM2 has been asserted.

DVDDP1_ERR

RWC

Dynamic Vccp Limit Error.

S3, S4/5

This bit is set if AD_IN7 (P1_Vccp) did not match the requested voltage as

reported by P1_VID[5:0].

DVDDP2_ERR

RWC

Dynamic Vccp Limit Error.

S3, S4/5

This bit is set if AD_IN8 (P2_Vccp) did not match the requested voltage as

reported by P1_VID[5:0].

D1_ERR

RWC

Diode Fault Error

S3*, S4/5*

This bit is set if there is an open or short circuit on the REMOTE1+ and

REMOTE1

− pins.

D2_ERR

RWC

Diode Fault Error

S3*, S4/5*

This bit is set if there is an open or short circuit on the REMOTE2+ and

REMOTE2

− pins.

3.17.4.5 Register 44h

B_P1_PROCHOT Error Status

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

B_P1_PR

TMAX

OCHOT

PH1

44h

RWC

T100

T75

T50

T25

T12

00h

Error

_ERR

Status

Sleep

Bit

Name

R/W

Description

Masking

RWC

Set when P1_PROCHOT has had a throttled event. This bit is set for any amount

S3, S4/5

of PROCHOT throttling >0%.

T12

RWC

Set when P1_PROCHOT has throttled greater than or equal to 0.39% but less than

S3, S4/5

12.5%.

T25

RWC

Set when P1_PROCHOT has throttled greater than or equal to 12.5% but less than

S3, S4/5

25%.

T50

RWC

Set when P1_PROCHOT has throttled greater than or equal to 25% but less than

S3, S4/5

50%.

T75

RWC

Set when P1_PROCHOT has throttled greater than or equal to 50% but less than

S3, S4/5

75%.

T100

RWC

Set when P1_PROCHOT has throttled greater than or equal to 75% but less than

S3, S4/5

100%.

Functional Description

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