LM5025AMTCSLASHNOPB datasheet(3/23 Pages) TI1

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LM5025A

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SNVS293E – DECEMBER 2004 – REVISED MARCH 2013

Table 1. PIN DESCRIPTION (continued)

Name

Description

Application Information

CS1

Current sense input for cycle-by-

If CS1 exceeds 0.5V the outputs will go into Cycle-by-Cycle current

cycle limiting

limit. CS1 is held low for 50ns after OUT_A switches high providing

leading edge blanking.

CS2

Current sense input for soft restart

If CS2 exceeds 0.5V the outputs will be disabled and a softstart

commenced. The soft-start capacitor will be fully discharged and then

released with a pull-up current of 1µA. After the first output pulse (when

SS =1V), the SS charge current will revert back to 20µA.

TIME

Output overlap/Deadtime control

An external resistor (RSET) sets either the overlap time or dead time for

the active clamp output. An RSET resistor connected between TIME and

GND produces in-phase OUT_A and OUT_B pulses with overlap. An

RSET resistor connected between TIME and REF produces out-of-

phase OUT_A and OUT_B pulses with deadtime.

REF

Precision 5 volt reference output

Maximum output current: 10mA Locally decouple with a 0.1µF

capacitor. Reference stays low until the VCC UV comparator is satisfied.

VCC

Output from the internal high

If an auxiliary winding raises the voltage on this pin above the

voltage start-up regulator. The VCC regulation setpoint, the internal start-up regulator will shutdown,

voltage is regulated to 7.6V.

reducing the IC power dissipation.

OUT_A

Main output driver

Output of the main switch PWM output gate driver. Output capability of

3A peak sink current.

OUT_B

Active Clamp output driver

Output of the Active Clamp switch gate driver. Capable of 1.25A peak

sink current..

PGND

Power ground

Connect directly to analog ground.

AGND

Analog ground

Connect directly to power ground. For the WSON package option the

exposed pad is electrically connected to AGND.

Soft-start control

An external capacitor and an internal 20µA current source set the

softstart ramp. The SS current source is reduced to 1uA initially

following a CS2 over-current event or an over temperature event.

COMP

Input to the Pulse Width Modulator

An internal 5k

Ω resistor pull-up is provided on this pin. The external

opto-coupler sinks current from COMP to control the PWM duty cycle.

Oscillator timing resistor pin

An external resistor connected from RT to ground sets the internal

oscillator frequency.

SYNC

Oscillator UP/DOWN

The internal oscillator can be synchronized to an external clock with a

synchronization input

frequency 20% lower than the internal oscillator’s free running

frequency. There is no constraint on the maximum sync frequency.

UVLO

Line Under-Voltage shutdown

An external voltage divider from the power source sets the shutdown

comparator levels. The comparator threshold is 2.5V. Hysteresis is set

by an internal current source (20µA) that is switched on or off as the

UVLO pin potential crosses the 2.5V threshold.

Exposed pad, underside of the

Internally bonded to the die substrate. Connect to GND potential for low

WSON package option

thermal impedance.

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