TLK2501

1.5 TO 2.5 GBPS TRANSCEIVER

SLLS427D − AUGUST 2000 − REVISED JULY 2003

9

POST OFFICE BOX 655303

detailed description (continued)

high-speed data output

The high-speed data output driver consists of a current-mode logic (CML) differential pair that can be optimized

for a particular transmission line impedance and length. The line can be directly-coupled or ac-coupled. Refer

to Figure 15 and Figure 16 for termination details.

receive interface

The receiver portion of the TLK2501 accepts 8-bit/10-bit encoded differential serial data. The interpolator and

clock recovery circuit locks to the data stream and extract the bit rate clock. This recovered clock is used to

retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit

decoded, and output on a 16-bit wide parallel bus synchronized to the extracted receive clock.

receive data bus

The receive bus interface drives 16-bit wide single-ended TTL parallel data at the RXD[0:15] terminals. Data

is valid on the rising edge of the RX_CLK when the RX_DV/LOS is asserted high and the RX_ER is deasserted

low. The RX_CLK is used as the recovered word clock. The data, enable, and clock signals are aligned as shown

in Figure 4. Detailed timing information can be found in the switching characteristics table.

RX_CLK

RXDn, RX_DV, RX_ER

tsu

th

Figure 4. Receive Timing Waveform

data reception latency

The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output

in the aligned parallel word with RXD0 received as first bit. The receive latency is fixed once the link is

established. However, due to silicon process variations and implementation variables such as supply voltage

maximum is 107 bit times. Figure 5 illustrates the timing relationship between the serial receive terminals, the

recovered word clock (RX_CLK), and the receive data bus.

16-Bit Decoded Word

20-Bit Encoded Word

DINTXP,

DINTXN

RXD(0−15)

RX_CLK

td(Rx latency)

Figure 5. Receiver Latency