DP84902MS datasheet(12/16 Pages) NSC

12 / 16 page

Functional Description

The EncoderDecoder (ENDEC) translates NRZ data to and

from the (17) RLL format receives and transfers NRZ data

in a 2-bit format generates code output that can be made

either TTL or ECL compatible indicates the need to pre-

compensate write data and issues READREFERENCE

CLOCK (RRCLK) READREFERENCE CLOCK multiplex-

ing is done without glitches

Control Register

The control register is comprised of a fourteen-bit serial shift

(Figure 11) Information is

strobed into the shift register via the CONTROL REGISTER

DATA (CRD) input on the positive edge of the CONTROL

TER LATCHSHIFT BAR (CRLS) pin at a logical low state

The information is parallel transmitted to the latch bank and

the ENDEC when the CRLS input is taken to a logical high

state The control register truth table (Table I) describes the

functions controlled by each bit in the control register The

bit at the right of each bit stream (13) in the table is the first

bit entered into the shift register

Two bits of the control register (bits 12) control the power

down option The other bits of the control register determine

various aspects of the ENDEC’s outputs Bit4 inverts the

sense of the CODEOUT output data Bit 6 changes CODE-

OUT from a TTL compatible output to a ECL (differential)

compatible output Bits 7 8 controls bypass selection No

bypass can be selected (bit7 e bit8 e 0) the precompen-

sation circuit can be bypassed (bit7 e 0 bit8 e 1) and the

CODEOUT pin can be tri-stated (bit7 e bit8 e 1) Bit 9

permits the use of an internal write clock Bit 10 must be set

to 1 for normal operation Bit 11 puts the encoder in a by-

pass mode if bit 7 and bit 8 are also set to 0 In this mode

the data received at the NRZIO0 pin will pass through the

encoder to the CODEOUT pin All of the reserved bits (0 3

5 12 13) are to be programmed at a logical low level

TLF11963 – 8

FIGURE 11 CTRL Register Block Diagram

TABLE I Control Register Truth Table

BIT STREAM

Function Selected

LSB

MSB

012345678910111213

xxxxxxxxx

Reserved Bit

xxxxxxx

Normal Operation

xxxxxxx

Power Down

Reserved Bit

Inverts CODEOUT Data

xxxxx

xxx

Reserved Bit

xxxxxx

xxx

Differential CODEOUT Data

xxxxxxx

No Bypass

xxxxxxx

Bypass Precompensation Circuit

xxxxxxx

TRI-STATE CODEOUT Pin

xxxxxxxxx

Use Internal Write Clock

xxxxxxxxxx

Normal Operation

xxxxxxx

Bypass Encoder

xxxxxxxxxx

Reserved Bit

xxxxxxxxxx

Reserved Bit

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