DP8441VLJ-40 datasheet(8/46 Pages) NSC

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30 Signal Descriptions (Continued)

32 DRAM CONTROL SIGNALS

Device (if not

Input

Description

Name

Applicable to All)

Output

Q0 – 11

DP8440

DRAM ADDRESS

These output signals are the multiplexed outputs of the R0 – 1112 and

C0 – 1112 and form the DRAM address bus These outputs contain the refresh address

Q0 – 12

DP8441

whenever RFIP is asserted They have high capacitive drivers with 20Xs series damping

resistors

RAS0–3

ROW ADDRESS STROBES

These outputs are asserted to latch the row address

contained on the outputs Q0 – 1112 into the DRAM When RFIP is asserted the RAS

outputs are used to latch the refresh row address contained on the Q0 – 1112 outputs into

the DRAM These outputs have high capacitive drivers with 20X series damping resistors

CAS0 – 3

DP8440

COLUMN ADDRESS STROBES

These outputs are asserted to latch the column address

contained on the outputs Q0 – 1112 into the DRAM When RFIP is asserted and CAS-

CAS0 – 7

DP8441

before-RAS refresh is selected the CAS outputs will assert 1T (one clock period) before

the RAS outputs are asserted These outputs have high capacitive drivers with 20X series

damping resistors

WRITE ENABLE

This output asserted specifies a write operation to the DRAM When

negated this output specifies a read operation to the DRAM This output has a high

capacitive driver and a 20X series damping resistor

WIN

WRITE ENABLE IN

This input is used to signify a write operation to the DRAM The WE

output will follow this input Also this input controls the precharge time for Read and Write

during Burst Mode Access

33 REFRESH SIGNALS

Device (if not

Input

Description

Name

Applicable to All) Output

RFRQ

REFRESH REQUEST

When RFRQ is asserted it specifies that 15 msor120 ms have

passed If DISRFSH is negated and the controller is not into an access cycle the

DP844041 will perform an internal refresh If DISRFSH is asserted RFRQ can be used to

externally request a refresh by asserting the input RFSH

RFIP

REFRESH IN PROGRESS

This output is asserted prior to a refresh cycle and is negated

when all the RAS outputs are negated for that refresh

RFSH

REFRESH

This input asserted with DISRFSH already asserted will request a refresh If

this input is continually asserted the DP844041 will perform refresh cycles in a burst

refresh fashion until the input is negated If RFSH is asserted with DISRFSH negated the

internal refresh address counter is cleared This technique is useful for burst refreshes

DISRFSH

DISABLE REFRESH

This input is used to disable internal refreshes and must be asserted

when using RFSH for externally requested refreshes

34 RESET AND PROGRAMMING SIGNALS

Device (if not

Input

Description

Name

Applicable to All)

Output

MODE LOAD

This input signal when low enables the internal programming register that

stores the programming information

RESET

SYSTEM RESET

Reset forces the DP844041 to be set at a known state VCC CLK and

DELCLK have to reach their proper DC and AC specifications for at least 1 ms before

negating the RESET signal All outputs are negated when RESET is asserted

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