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SN74LVC1G175DBVT bảng dữ liệu(PDF) 1 Page - Texas Instruments

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tên linh kiện SN74LVC1G175DBVT
Giải thích chi tiết về linh kiện  SINGLE D-TYPE DFLIP FLOP WITH ASYNCHRONOUS CLEAR
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SN74LVC1G175
SINGLE DTYPE FLIPFLOP
WITH ASYNCHRONOUS CLEAR
SCES560A − MARCH 2004 − REVISED AUGUST 2004
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
D Available in the Texas Instruments
NanoStar
 and NanoFree Packages
D Supports 5-V VCC Operation
D Inputs Accept Voltages to 5.5 V
D Max tpd of 4.3 ns at 3.3 V
D Low Power Consumption, 10-µA Max ICC
D ±24-mA Output Drive at 3.3 V
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D)
is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low
state, regardless of the clock edge or data on D.
NanoStar
 and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
NanoStar
 − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Reel of 3000
SN74LVC1G175YEPR
_ _ _D6_
−40 C to 85 C
NanoFree
 − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Reel of 3000
SN74LVC1G175YZPR
_ _ _D6_
−40
°C to 85°C
SOT (SOT-23) − DBV
Reel of 3000
SN74LVC1G175DBVR
C75_
SOT (SOT-23) − DBV
Reel of 250
SN74LVC1G175DBVT
C75_
SOT (SC-70) − DCK
Reel of 3000
SN74LVC1G175DCKR
D6_
SOT (SC-70) − DCK
Reel of 250
SN74LVC1G175DCKT
D6_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb,
• = Pb-free).
Copyright
 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
6
5
4
CLK
GND
D
CLR
VCC
Q
3
2
1
4
5
6
D
GND
CLK
Q
VCC
CLR
YEP OR YZP PACKAGE
(BOTTOM VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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