PC87393 datasheet(29/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.2.3

Standard Logical Device Configuration Register Definitions

In the registers below, any undefined bit is reserved. Unless otherwise noted, the following definitions also hold true:

All registers are read/write.

All reserved bits return 0 on reads, except where noted otherwise. To prevent unpredictable results, do not modify

these bits. Use read-modify-write to prevent the values of reserved bits from being changed during write.

Write only registers should not use read-modify-write during updates.

Table 7. Standard Control Registers

Table 8. Logical Device Activate Register

Note: When the X-Bus Extension is disabled, access to its registers (not the PnP registers) is disabled, but all bridging func-

tions continue to operate according to its register settings.

Table 9. I/O Space Conﬁguration Registers

Index

Description

07h

Logical Device

Number

This register selects the current logical device. See Table 6 for valid numbers. All

other values are reserved.

20h - 2Fh

SuperI/O

Conﬁguration

SuperI/O conﬁguration registers and ID registers

Index

Description

30h

Activate

Bit 0 - Logical device activation control

0: Disabled

1: Enabled

Bits 7-1 - Reserved

Index

Description

60h

I/O Port Base

Address Bits (15-8)

Descriptor 0

Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0.

61h

I/O Port Base

Address Bits (7-0)

Descriptor 0

Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0.

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