CPC75282KA datasheet(14/19 Pages) IXYS

14 / 19 page

PRELIMINARY

INTEGRATED CIRCUITS DIVISION

CPC75282

PRELIMINARY

R00E

Break-before-make operation occurs when the ringing

switches open before the break switches, SW1 and

SW2, close.

2.3.5: Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B

2.3.6 Break -Before- Make Operation

Break-before-make operation can be achieved using

OFFx to disable all of the switches when pulled to a

logic low. Although logically disabled, an active

(closed) ringing switch, SW4, will remain closed until

the next zero crossing current event.

Pull OFFx to a logic low to end the ringing state.

This opens the ringing return switch, SW3, and

prevents any other switches from closing.

Keep OFFx low for at least one-half the duration

of the ringing cycle period to allow sufficient time

for a zero crossing current event to occur and for

the circuit to enter the break-before-make state.

During the OFFx low period, set the P1, P2, and

P3 inputs to the idle/talk state.

Release OFFx , allowing the internal pull-up to

activate the break switches.

2.4 Data Latch

The CPC75282 has integrated transparent data

latches. The latch enable operation is controlled by

logic input levels at the LATCHx pin. Data input to the

latch is via the input pins P1, P2, and P3 while the

outputs of the data latch are internal nodes used for

state control. When the latch enable control pin is at a

logic 0 the data latch is transparent and the input

control signals flow directly through the data latch to

the state control circuitry. A change in input will be

reflected by a change in the switch states.

Whenever the latch enable control pin is at logic 1, the

data latch is active and data is locked. Subsequent

changes to the input controls P1, P2, and P3 will not

result in a change to the control logic or affect the

existing switch states.

The switches will remain in the state they were in

when the LATCHx changes from logic 0 to logic 1, and

will not respond to changes in input as long as the

LATCHx is at logic 1. However, neither the TSDx nor

the OFFx are affected by the latch function. Since

internal thermal shutdown control and external OFFx

control is not affected by the state of the latch enable

input, TSDx and OFFx will override state control.

2.5 TSD Pin Description

The TSDx pins are bidirectional I/O structures with

internal pull-up resistors sourced from VDD. As

outputs, these pins indicate the status of the thermal

shutdown circuitry for the associated channels.

Typically, during normal operation, these pins will be

pulled up to VDD , but, under fault conditions that

create excess thermal loading, the channels will enter

thermal shutdown and a logic low will be output.

As inputs, the TSDx pins are utilized to place the

channel into the All-Off state by simply pulling the

input low. For applications using low-voltage logic

devices (lower than VDD), IXYS Integrated Circuits

Division recommends the use of an open-collector or

an open-drain type output to control TSDx. This avoids

State

CFG=0, P3=0

LATCHx OFFx

Timing

Break

Switches

1x & 2x

Ringing

Return

Switch

Ringing

Switch

Test

Switches

5x & 6x

Ringing

Off

All-Off

Hold this state for at least one-half of the

ringing cycle. SW4 waiting for zero

current to turn off.

Off

All-Off

Zero current has occurred.

SW4 has opened

OffOffOffOff

Talk

Break switches close.

Off

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