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This register controls the various operating modes available for the transceiver and ENDEC functions. This register will

affect the operation of ALL ports of the 4TPhy.

Table 13. Global Control/Mask Register, addr = 08h

D15 : D14

D13

D12

D11

D10

D9

D8 : D3

D2

D1

D0

RESV

LNKJABINT AUTOSW TPIAUI HBEN ENPOLSW

RESV

KLED LJINTMASK GATERXC

Name

Bit

Reset

Value

Description

Type

resv

D15-14

0

Reserved; must be written with ‘0’.

R/W

LNKJABINT

D13

0

Link Jabber Interrupt Status; This bit is set when an interrupt occurs

due to a link status change or a jabber condition on any port. This bit

is cleared on a register read (the interrupt is also cleared).

R

AUTOSW

D12

1

Auto Switching; If this bit is set, automatic selection of TPI or AUI on

port 1 is enabled. If reset, port 1 configuration is determined by the

TPIAUI bit.

R/W

TPIAUI

D11

1

TPI Select; If this bit is set, then port 1 is placed into TP mode. If reset,

then port 1 is configured for AUI mode.

This bit is ignored if the AUTOSW bit is set.

R/W

HBEN

D10

1

Heartbeat Enable; If this bit is set, then heartbeat is enabled. If reset,

it is disabled for all ports.

R/W

ENPOLSW

D9

1

Enable Polarity Switching; If this bit is set, then auto polarity detec-

tion and correction is enabled for all ports. If reset, it is disabled.

R/W

MAC I/F

D[8:6]

Strap

RXD[3:1]

MAC Interface selection; Selects between one of 5 Serial NRZ MAC

interface protocols. See the table in the Interface Description chapter

for details on the different modes.

R/W

resv

D5

0

Reserved; must be written with ‘0’.

R/W

RXD_IDLE

D4

Opposite

of strap

option

LINK_1

RXD Level During Idle - selects the level of RXD during Rx Idle (CRS

deasserted). ‘1’ selects RXD_IDLE = High, ‘0’ selects RXD_IDLE=

Low. Default condition is for RXD to be low during Idle.The reset value

is determined by the mode selected by the LINK_1 pin and is opposite

of the strap value. (i.e. if strap LINK_1 =’1’ then reset value of this bit

= ‘0’)

R/W

resv

D3

0

Reserved; must be written with ‘0’.

R/W

KLED

D2

0

Enhanced LED Mode; If this bit is set, “enhanced” LED mode is se-

lected. If reset, “normal” LED mode is selected.

R/W

LJINTMASK

D1

0

Link Jabber Interrupt Mask; If this bit is set, an interrupt will NOT be

generated on a link-fail or jabber condition experienced on any port. If

reset, interrupt generation is enabled.

R/W

GATERXC

D0

Strap

COL[4]

RXC Gated; If this bit is set, five RXC clocks are forced after CRS is

deasserted. If reset, then RXC clocks are continuous after CRS deas-

serts.

R/W