ADUC841 datasheet(23/88 Pages) AD

23 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 23 of 88

ADC CIRCUIT INFORMATION

General Overview

The ADC conversion block incorporates a fast, 8-channel,

12-bit, single-supply ADC. This block provides the user with

multichannel mux, track-and-hold, on-chip reference, calibra-

tion features, and ADC. All components in this block are easily

configured via a 3-register SFR interface.

The ADC converter consists of a conventional successive

approximation converter based around a capacitor DAC. The

converter accepts an analog input range of 0 V to VREF. A high

precision, 15 ppm, low drift, factory calibrated 2.5 V reference is

provided on-chip. An external reference can be connected as

described in the Voltage Reference Connections section. This

external reference can be in the range 1 V to AVDD.

Single-step or continuous conversion modes can be initiated in

software or alternatively by applying a convert signal to an

external pin. Timer 2 can also be configured to generate a

repetitive trigger for ADC conversions. The ADC may be

configured to operate in a DMA mode whereby the ADC block

continuously converts and captures samples to an external

RAM space without any interaction from the MCU core. This

automatic capture facility can extend through a 16 MByte

external data memory space.

The ADuC841/ADuC842/ADuC843 are shipped with factory

programmed calibration coefficients that are automatically

downloaded to the ADC on power-up, ensuring optimum ADC

performance. The ADC core contains internal offset and gain

calibration registers that can be hardware calibrated to

minimize system errors.

A voltage output from an on-chip band gap reference propor-

tional to absolute temperature can also be routed through the

front end ADC multiplexer (effectively a 9th ADC channel

input), facilitating a temperature sensor implementation.

ADC Transfer Function

The analog input range for the ADC is 0 V to VREF. For this

range, the designed code transitions occur midway between

successive integer LSB values, i.e., 0.5 LSB, 1.5 LSB, 2.5 LSB . . .

FS –1.5 LSB. The output coding is straight binary with 1 LSB =

FS/4096 or 2.5 V/4096 = 0.61 mV when VREF = 2.5 V. The ideal

input/output transfer characteristic for the 0 V to VREF range is

shown in Figure 28.

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...010

000...001

000...000

0V 1LSB

+FS

1LSB =

4096

Figure 28. ADC Transfer Function

Typical Operation

Once configured via the ADCCON 1–3 SFRs, the ADC converts

the analog input and provides an ADC 12-bit result word in the

ADCDATAH/L SFRs. The top 4 bits of the ADCDATAH SFR

are written with the channel selection bits to identify the channel

result. The format of the ADC 12-bit result word is shown in

Figure 29.

CH–ID

TOP 4 BITS

HIGH 4 BITS OF

ADC RESULT WORD

LOW 8 BITS OF THE

ADC RESULT WORD

ADCDATAH SFR

ADCDATAL SFR

Figure 29. ADC Result Word Format

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