ADT7461

serial bus in a single read or write operation is limited only

by what the master and slave devices can handle.

3.

When all data bytes have been read or written, stop condi-

tions are established. In write mode, the master will pull the

data line high during the tenth clock pulse to assert a STOP

condition. In read mode, the master device will override

the acknowledge bit by pulling the data line high during

the low period before the ninth clock pulse. This is known

as No Acknowledge. The master will then take the data line

low during the low period before the tenth clock pulse,

then high during the tenth clock pulse to assert a STOP

condition.

Any number of bytes of data may be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation. In the case of the ADT7461, write

operations contain either one or two bytes, while read opera-

tions contain one byte.

To write data to one of the device data registers or to read

data from it, the address pointer register must be set so that the

correct data register is addressed. The first byte of a write opera-

tion always contains a valid address that is stored in the address

pointer register. If data is to be written to the device, the write

operation contains a second data byte that is written to the

register selected by the address pointer register.

This is illustrated in

. The device address is sent over

the bus followed by R/W set to 0. This is followed by two data

bytes. The first data byte is the address of the internal data

register to be written to, which is stored in the address pointer

register. The second data byte is the data to be written to the

internal data register.

Figure 15

Figure 15. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

A6

19

1

A5

A4

A3

A2

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

SCLK

SDAT

9

A

START BY

MASTER

ACK. BY

ADT7461

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 3

DATA BYTE

SCLK (CONTINUED)

SDATA (CONTINUED)

ACK. BY

ADT7461

ACK. BY

ADT7461

STOP BY

MASTER

9

1

D7

D6

D5

D4

D3

D2

D1

D0

SCLK

SDATA

START BY

MASTER

ACK. BY

ADT7461

ACK. BY

ADT7461

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

19

1

A6

A5

A4

A3

A2

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

9

Figure 16. Writing to the Address Pointer Register Only

SCLK

SDATA

START BY

MASTER

ACK. BY

ADT7461

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

DATA BYTE FROM ADT7461

ACK. BY

ADT7461

STOP BY

MASTER

19

1

9

A6

A5

A4

A3

A2

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

Figure 17. Reading from a Previously Selected Register

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