TMS320DM355CZCEA21 datasheet(2/163 Pages) TI1

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TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

www.ti.com

With 256 MByte Address Space (1.8-V I/O)

– S/PDIF via Software

– Asynchronous16-/8-bit Wide EMIF (AEMIF)

– Standard Voice Codec Interface (AIC12)

•

Flash Memory Interfaces

– SPI Protocol (Master Mode Only)

–

NAND (8-/16-bit Wide Data)

• Four Pulse Width Modulator (PWM) Outputs

–

OneNAND(16-bit Wide Data)

• Four RTO (Real Time Out) Outputs

• Flash Card Interfaces

• Up to 104 General-Purpose I/O (GPIO) Pins

(Multiplexed with Other Device Functions)

– Two Multimedia Card (MMC) / Secure Digital

(SD/SDIO)

• On-Chip ARM ROM Bootloader (RBL) to Boot

From NAND Flash (with SPI EEPROM Boot

– SmartMedia

option), MMC/SD, or UART

• Enhanced Direct-Memory-Access (EDMA)

• Configurable Power-Saving Modes

Controller (64 Independent Channels)

• Crystal or External Clock Input (typically

• USB Port with Integrated 2.0 High-Speed PHY

24 MHz or 36 MHz)

that Supports

• Flexible PLL Clock Generators

– USB 2.0 Full and High-Speed Device

• Debug Interface Support

– USB 2.0 Low, Full, and High-Speed Host

– IEEE-1149.1 (JTAG)

• Three 64-Bit General-Purpose Timers (each

Boundary-Scan-Compatible

configurable as two 32-bit timers)

– ETB™ (Embedded Trace Buffer™) with

• One 64-Bit Watch Dog Timer

4K-Bytes Trace Buffer memory

• Three UARTs (One fast UART with RTS and

– Device Revision ID Readable by ARM

CTS Flow Control)

• 337-Pin Ball Grid Array (BGA) Package

• Three Serial Port Interfaces (SPI) each with two

(ZCE Suffix), 0.65-mm Ball Pitch

Chip-Selects

• 90nm Process Technology

• One Master/Slave Inter-Integrated Circuit (I2C)

Bus®

• 3.3-V and 1.8-V I/O, 1.3-V Internal

• Two Audio Serial Port (ASP)

• Community Resources

– I2S and TDM I2S

– TI E2E Community

– AC97 Audio Codec Interface

– TI Embedded Processors Wiki

TMS320DM355 Digital Media System-on-Chip (DMSoC)

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Product Folder Link(s): TMS320DM355

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