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DP83902AVF bảng dữ liệu(PDF) 34 Page - National Semiconductor (TI) |
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DP83902AVF bảng dữ liệu(HTML) 34 Page - National Semiconductor (TI) |
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34 / 70 page ![]() 100 Internal Registers (Continued) 104 DMA REGISTERS DMA Registers TLF11157 – 19 The DMA Registers are partitioned into groups Transmit Receive and Remote DMA Registers The Transmit regis- ters are used to initialize the Local DMA Channel for trans- mission of packets while the Receive Registers are used to initialize the Local DMA Channel for packet Reception The Page Stop Page Start Current and Boundary Registers are used by the Buffer Management Logic to supervise the Re- ceive Buffer Ring The Remote DMA Registers are used to initialize the Remote DMA Note In the figure above registers are shown as 8 or 16 bits wide Although some registers are 16-bit internal registers all registers are accessed as 8-bit registers Thus the 16-bit Transmit Byte Count Register is broken into two 8-bit registers TBCR0 TBCR1 Also TPSR PSTART PSTOP CURR and BNRY only check or control the upper 8 bits of address information on the bus Thus they are shifted to positions 15–8 in the diagram above 105 TRANSMIT DMA REGISTERS TRANSMIT PAGE START REGISTER (TPSR) This register points to the assembled packet to be transmit- ted Only the eight higher order addresses are specified since all transmit packets are assembled on 256-byte page boundaries The bit assignment is shown below The values placed in bits D7 – D0 will be used to initialize the higher order address (A8 – A15) of the Local DMA for transmission The lower order bits (A7 – A0) are initialized to zero Bit Assignment 76543210 TPSR A15 A14 A13 A12 A11 A10 A9 A8 (A7–A0 Initialized to Zero) TRANSMIT BYTE COUNT REGISTER 0 1 (TBCR0 TBCR1) These two registers indicate the length of the packet to be transmitted in bytes The count must include the number of bytes in the source destination length and data fields The maximum number of transmit bytes allowed is 64 Kbytes The ST-NIC will not truncate transmissions longer than 1500 bytes The bit assignment is shown below 76543210 TBCR1 L15 L14 L13 L12 L11 L10 L9 L8 76543210 TBCR0 L7 L6 L5 L4 L3 L2 L1 L0 34 |
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