MSP50C30

MIXED-SIGNAL PROCESSOR

SPSS021 NOVEMBER 1998

6

POST OFFICE BOX 655303

switching characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tr

Rise time

PA, PB, PC,

PD, D/A

VDD = 3.3 V,

CL = 100 pF,

10% to 90%

50

ns

tr

Rise time

OA

VDD = 3.3 V,

CL = 50 pF,

10% to 90%

50

ns

tf

Fall time

PA, PB, PC,

PD, D/A

VDD = 3.3 V,

CL = 100 pF,

10% to 90%

50

ns

tf

Fall time

OA

VDD = 3.3 V,

CL = 50 pF,

10% to 90%

50

ns

timing requirements

MIN

MAX

UNIT

Initialization

tINIT

INIT pulsed low while the MSP50x3x has power applied (see Figure 1)

1

µs

Wakeup

tsu(wakeup)

Setup time prior to wakeup terminal negative transition (see Figure 2)

1

µs

External Interrupt

t

(i t

t)

Setup time prior to B1 terminal negative transition (see Figure 3)

fclock = 15.36 MHz

1

µs

tsu(interrupt) Setup time prior to B1 terminal negative transition (see Figure 3)

fclock = 19.2 MHz

1.5

µs

Writing (Slave Mode)

tsu1(B1)

Setup time, B1 low before B0 goes low (see Figure 4)

20

ns

tsu(d)

Setup time, data valid before B0 goes high (see Figure 4)

100

ns

th1(B1)

Hold time, B1 low after B0 goes high (see Figure 4)

20

ns

th(d)

Hold time, data valid after B0 goes high (see Figure 4)

30

ns

tw

Pulse duration, B0 low (see Figure 4)

100

ns

tr

Rise time, B0 (see Figure 4)

50

ns

tf

Fall time, B0 (see Figure 4)

50

ns

Reading (Slave Mode)

tsu2(B1)

Setup time, B1 before B0 goes low (see Figure 5)

20

ns

th2(B1)

Hold time, B1 after B0 goes high (see Figure 5)

20

ns

tdis

Output disable time, data valid after B0 goes high (see Figure 5)

0

30

ns

tw

Pulse duration, B0 low (see Figure 5)

100

ns

tr

Rise time, B0 (see Figure 5)

50

ns

tf

Fall time, B0 (see Figure 5)

50

ns

td

Delay time for B0 low to data valid (see Figure 5)

50

ns

External ROM

ta(ROM)

ROM access time

400

ns