DP83907VF datasheet(50/70 Pages) NSC

50 / 70 page

60 Operation of DP83907 (Continued)

CRC and Address Recognition

The next three tests exercise the address recognition logic

and CRC These tests should be performed using internal

Ioopback only so that the DP83907 is isolated from interfer-

ence from the network These tests also require the capabil-

ity to generate CRC in software

The address recognition logic cannot be directly tested The

CRC and FAE bits in the RSR are only set if the address if

the packet matches the address filters If errors are expect-

ed to be set and they are not set the packet has been

rejected on the basis of an address mismatch The following

sequence of packets will test the address recognition logic

The DCR should be set to 40H the TCR should be set to

03H with a software generated CRC

Packet Contents

Results

Test

Address

CRC

RSR

Test A

Matching

Good

01 (Note 1)

Test B

Matching

Bad

02 (Note 2)

Test C

Non-Matching

Bad

Note 1

Status will read 21H if multicast address used

Note 2

Status will read 22H if multtcast address used

Note 3

In test A the RSR is set up In test B the address is found to match

since the CRC is flagged as bad Test C proves that the address recognition

logic can distinguish a bad address and does not notify the RSR of the bad

CRC The receiving CRC is proven to work in test A and test B

Note 4

All values are hex

TLF12082 – 31

FIGURE 36 Tally Counters

Network Management Functions

Network management capabilities are required for mainte-

nance and planning of a local area network The DP83907

supports the minimum requirement for network manage-

ment in hardware the remaining requirements can be met

with software Software alone can not track during reception

of packets

CRC errors

Frame Alignment errors

and

missed packets

Figure 36

Since errored packets can be rejected the status associat-

ed with these packets is lost unless the CPU can access the

Receive Status Register before the next packer arrives In

situations where another packet arrives very quickly the

CPU may have no opportunity to do this The DP83907 Con-

troller counts the number of packets with CRC errors and

Frame Alignment errors 8-bit counters have been selected

to reduce overhead The counters will generate interrupts

whenever their MSBs are set so that a software routine can

accumulate the network statistics and reset the counter be-

tore overflow occurs The counters are sticky so that when

they reach a count of 192 (C0H) counting is halted An addi-

tional counter is provided to count the number of packets

the DP83907 misses due to buffer overflow or being off-line

The structure of the counters is shown in

Figure 36

Additional information required for network management is

available in the Receive and Transmit Status Registers

Transmit status is available after each transmission for infor-

mation regarding events during transmission

Typically the following statistics might be gathered in soft-

ware

Traffic

Frames Sent OK

Frames Received OK

Multicast Frames Received

Packets Lost Due to Lack of

Resources

RetriesPacket

Errors

CRC Errors

Alignment Errors

Excessive Collisions

Packet with Length Errors

Heartbeat Failure

66 MEMORY ARBITRATION AND BUS OPERATION

The DP83907 will always operate as a slave device on it’s

peripheral interface to the ISA bus However on the memory

bus the DP83907 Controller operates in three possible

modes

1 Bus Master of Local Packet Buffer RAM

2 Bus Slave when accessed by the CPU via the Bus Inter-

face

3 Idle when no activity is occurring

TLF12082 – 32

FIGURE 37 DP8390 Core Bus States

Upon power-up the DP83907 is in an indeterminate state

After receiving a hardware reset the DP83907 is a bus slave

in the Reset State the receiver and transmitter are both

disabled in this state The reset state can be re-entered

under four conditions soft reset (Stop Command) register

reset (reset port) hard reset (RESET input) or an error that

shuts down the receiver of transmitter (FIFO underflow or

overflow receive buffer ring overflow)

After initialization of registers the DP83907 Controller is is-

sued a Start command and the DP83907 enters Idle state

Until the DMA is required the DP83907 remains in idle state

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