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ADF7020 bảng dữ liệu(PDF) 6 Page - Analog Devices |
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ADF7020 bảng dữ liệu(HTML) 6 Page - Analog Devices |
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6 / 40 page ![]() ADF7020 Preliminary Technical Data Rev. PrH | Page 6 of 40 Parameter Min Typ Max Unit Test Conditions PLL Settling Time 40 µs Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = TBD REFERENCE INPUT Crystal Reference 3.625 24 MHz External Oscillator 3.625 24 MHz Load capacitance TBD pF Input Level CMOS levels See the Reference Input Section TIMING INFORMATION Chip Enabled to Regulator Ready TBD µs CREG = 100 nF Crystal Oscillator Startup time 1 ms With 19.2 MHz XTAL Tx to Rx Turnaround Time 350 µs + (5 × TBIT) Time to synchronized data, includes AGC settling LOGIC INPUTS VINH, Input High Voltage 0.7 × V DD V VINL, Input Low Voltage 0.2 × V DD V IINH/IINL, Input Current ±1 µA CIN, Input Capacitance 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS VOH,Output High Voltage DVDD − 0.4 V IOH = 500 µA VOL, Output Low Voltage 0.4 V IOL = 500 µA CLKOUT Rise/Fall 5 ns CLKOUT Load 10 pF TEMPERATURE RANGE—TA −40 +85 °C POWER SUPPLIES Voltage Supply AVDD 2.3 3.6 V DVDD AVDD AVDD Transmit Current Consumption FRF = 915 MHz, VDD = 3.0 V, PA is matched in to 50 Ω −20 dBm TBD mA −10 dBm 12 mA VCO_BIAS_SETTING = 3 0 dBm 15 mA 10 dBm 22 mA Receive Current Consumption Low Current Mode 19 TBD mA High Sensitivity Mode 21 TBD mA Power-Down Mode Low Power Sleep Mode 0.1 1 µA 1 Higher data rates are achievable depending on local regulations. 2 For definition of frequency deviation, see the R section. egister 2—Transmit Modulation Register (FSK Mode) 3 For definition of GFSK frequency deviation, see the R section. egister 2—Transmit Modulation Register (GFSK/GOOK Mode) 4 Measured as maximum unmodulated power. Output power varies with both supply and temperature. 5 For matching details, see the LN section. A/PA Matching 6 See Table 5 for description of different receiver modes. 7 See Table 5 for description of different receiver modes. 8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications. 9 See the section. Image Rejection Calibration |
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