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DP83905AVQB bảng dữ liệu(PDF) 61 Page - National Semiconductor (TI) |
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DP83905AVQB bảng dữ liệu(HTML) 61 Page - National Semiconductor (TI) |
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61 / 80 page ![]() 60 Operation of ATLANTIC Controller (Continued) Shared Memory Mode Write Bus Timing with DWID Low TLF11498 – 44 This is the type of cycle used to write to buffer RAM in shared memory mode when DWlD is low These accesses are entirely asynchronous with the ATLANTIC Controller responding when it decodes the address on SA0 – 19 matches Control Register 1 and an SMWR If AEN is high the cycle will be ignored CHRDY is deasserted if the ATLANTIC Controller is not ready to respond and asserted when ready If it is ready immediately CHRDY is not deasserted If the memory width bit in Control Register 2 is low then 8 kbytes of RAM are accessible so only RCS1 is used to strobe data and the data is always on MSD0 – 7 If this bit is high 16 kbytes of RAM are accessible so both chip selects and byte lanes are used If the memory address is even RCS1 and MSD0 – 7 are used if odd RCS2 and MSD8 – 15 are used System data is always taken from SD0 – 7 61 |
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