CLC5903VLASLASHNOPB datasheet(21/31 Pages) TI1

21 / 31 page

www.national.com

level. DVGA operation results in a compression of the signal

through the ADC. The DVGA signal compression is reversed

in the CLC5903 to provide > 120dB of linear dynamic range.

This is illustrated in Figure 32.

In order to use the AGC, the DRCS Control Panel software

may be used to calculate the programmable parameters. To

generate these parameters, only the desired setpoint, dead-

band+hysteresis, and loop time constant need to be sup-

plied. All subsequent calculations are performed by the

software. Complete details of the AGC operation are pro-

vided in an appendix but are not required reading.

AGC setpoint and deadband+hysteresis are illustrated in Fig-

ure 33. The loop time constant is a measure of how fast the

loop will track a changing signal. Values down to approxi-

mately 1.0 microsecond will be stable with the second order

LC noise filter. Since the DVGA operates with 6dB steps the

deadband should always be greater than 6dB to prevent

oscillation. An increased deadband value will reduce the

amount of AGC operation. A decreased deadband value will

increase the amount of AGC operation but will hold the ADC

output closer to the setpoint. The threshold should be set so

that transients do not cause sustained overrange at the ADC

inputs. The threshold setting can also be used to set the

ADC input near its optimal performance level.

The AGC will free run when AGC_HOLD_IC is set to ‘0’. It

may be set to a fixed gain by setting AGC_HOLD_IC to ‘1’

after programming the desired gain in the AGC_IC_A and

AGC_IC_B registers. Allowing the AGC to free run should be

appropriate for most applications.

Programming the AGC_COMB_ORD register allows the

AGC power detector bandwidth to be reduced if desired. This

will tend to improve the power detector’s ability to reject the

signal carrier frequency and reduce overall AGC activity. Fig-

ure 36 on page 24 shows the power detector response.

Power Management

The CLC5903 can be placed in a low power (static) state by

stopping the input clock. To prevent this from placing the

CLC5903 into unexpected states, the SI pin of the CLC5903

should be asserted prior to disabling the input clock and held

asserted until the input clock has returned to a stable condi-

tion.

Test and Diagnostics

The CLC5903 supports IEEE 1149.1 compliant JTAG Bound-

ary Scan for the I/O's. The following pins are used:

TRST (test reset)

TMS

(test mode select)

TDI

(test data in)

TDO

(test data out)

TCK

(test clock)

The following JTAG instructions are supported:

The JTAG Boundary Scan can be used to verify printed cir-

cuit board continuity at the system level.

The user is able to program a value into TEST_REG and

substitute this for the normal channel inputs from the AIN/

BIN pins by selecting it with the crossbar. With the NCO fre-

quency set to zero this allows the DDCs and the output inter-

face of the chip to be verified. Also, the AGC loop can be

opened by setting AGC_HOLD_IC high and setting the gain

of the DVGA by programming the appropriate value into the

AGC_IC_A/B register.

Real-time access to the following signals is provided by con-

figuring the control interface debug register:

•

NCO sine and cosine outputs

•

data after round following mixers

•

data before F1 and F2

•

data after the CIC filter within the AGC

The access points are multiplexed to a 20-bit parallel output

port which is created from signal pins POUT[15:0], AOUT,

BOUT, SFS, and RDY according to the table below:

Figure 32. Output Gain Scaling vs. Input Signal

Input Power

ADC Output

ADC Full Scale

AGC Threshold

Deadband+Hysteresis

Diversity Receiver

Chipset Full Scale

Figure 33. AGC Setup.

DVGA Input Power

Deadband

Hysteresis=Deadband-6dB

Reference

6dB

Setpoint

Instruction

Description

BYPASS

Connects TDI directly to TDO

EXTEST

Drives the ‘extest’ TAP controller output

IDCODE

Connects the 32-bit ID register to TDO

SAMPLE/PRELOAD

Drives the ‘samp_load’ TAP controller

output

HIGHZ

Tri-states the outputs

Normal Mode Pin

Debug Mode Pin

POUT[15:0]

DEBUG[19..4]

RDY

DEBUG[3]

SFS

DEBUG[2]

AOUT

DEBUG[1]

BOUT

DEBUG[0]

Test and Diagnostics (Continued)

CLC5903VLA/NOPB bảng dữ liệu(PDF) 21 Page - Texas Instruments

CLC5903VLA/NOPB bảng dữ liệu(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

bảng dữ liệu tải về

Link URL