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DP83858VF bảng dữ liệu(PDF) 3 Page - National Semiconductor (TI) |
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DP83858VF bảng dữ liệu(HTML) 3 Page - National Semiconductor (TI) |
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3 / 37 page ![]() 3 http:\\www.national.com Table of Contents 1.0 Pin Connection Diagram 1.1 Pin Table 2.0 Pin Description 2.1 Physical Layer Interface 2.2 Inter Repeater and Management Bus Inter- face 2.3 EEPROM Interface 2.4 Miscellaneous 2.5 Pin Type Designation 3.0 Functional Description 3.1 Repeater State Machine 3.2 RXE Control 3.3 TXE Control 3.4 Data Path 3.5 Elasticity Buffer 3.6 Jabber Protection State Machine 3.7 Auto-Partition State Machine 3.8 Inter Repeater Bus Interface 3.9 Management Bus 3.10 Management Event Flags and Counters 3.11 Serial Register Interface 3.12 Jabber/Partition LED Driver Logic 3.13 EEPROM Serial Read Access 4.0 Registers 4.1 Page 0 Register Map 4.2 Page 1 Register Map 4.3 Configuration Register (CONFIG) 4.4 Page Register (PAGE) 4.5 Partition Status Register (PARTITION) 4.6 Jabber Status Register (JABBER) 4.7 Administration Register (ADMIN) 4.8 Device ID Register (DEVICEID) 4.9 Hub ID 0 Register (HUBID0) 4.10 Hub ID 1 Register (HUBID1) 4.11 Port Management Counter Registers 4.12 Silicon Revision Register (SIREV) 5.0 DP83858 Applications 5.1 MII Interface Connections 5.2 Repeater ID Interface 5.3 Inter Repeater Bus Connections 5.4 DP83856 100RIB Connections 5.5 Port Partition and Jabber Status LEDs 6.0 AC and DC Specifications 6.1 DC Specifications 6.2 AC Specifications 7.0 Physical Dimensions |
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