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4.4 Page Register (PAGE)

4.5 Partition Status Register (PARTITION)

4.6 Jabber Status Register (JABBER)

D1

PHY_ACCESS

r/w

This bit allows the management agent to access the DP83840A PHY chip’s register

via the MII serial protocol.

0:

PHY access disabled (default).

1:

PHY register access enabled.

Note: When in PHY_access mode, RDIO will be driven by the DP83850C during the

read phase for all read commands. This is to allow the DP83840A Physical Layer de-

vices to pass their data through their local DP83850C. While in this mode, contention

will result (on the RDIO line) if any device other than this DP83850C or the DP83840A

Physical Layer devices are accessed.

D0

RST_RSM

r/w

Setting this bit holds the Repeater State Machines in reset. The management event

flags and counters are unaffected by this bit. Setting this bit while a reception is in

progress may truncate the packet.

0:

DP83850C in normal operation (default).

1:

DP83850C held in reset.

Page 0

Address 1h

Page 1

Address 1h

Bit

Bit Name

Ac-

cess

Bit Description

D15 - D2 reserved

-

These bits are undefined when read. Must be written as 0.

D1 - D0 PAGE[1:0]

r/w

These bits program the register page to be accessed. The page encoding is as follows:

PAGE[1:0]

Page

0h

0

(default)

1h

1

2h

reserved

3h

reserved

Page 0

Address 2h

Bit

Bit Name

Access

Bit Description

D15 - D12 reserved

-

These bits are undefined when read.

D11 - D0

PART[11] ...

PART[0]

read only The respective port's PART bit is set to 1 when Partitioning is sensed on that port.

After reset, these bits are cleared to zero.

Page 0

Address 3h

Bit

Bit Name

Access

Bit Description

D15 - D12 reserved

-

These bits are undefined when read.

D11 - D0

JAB[11..0] read only The respective port's JAB bit is set to 1 when the Jabber condition is detected on that

port. After reset, these bits are cleared to zero.

Bit

Bit Name

Access

Bit Description