CD74AC20

DUAL 4INPUT POSITIVENAND GATES

SCHS229B – SEPTEMBER 1998 – REVISED NOVEMBER 2002

1

POST OFFICE BOX 655303

and Balanced Noise Immunity at 30% of the

Supply

Significantly Reduced Power Consumption

– Fanout to 15 F Devices

Circuit Design

MIL-STD-883, Method 3015

description/ordering information

The AC device contains two independent 4-input NAND gates. This device performs the Boolean function

Y = A

• B • C • D or Y = A + B + C + D in positive logic.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – E

Tube

CD74AC20E

CD74AC20E

–55

°C to 125°C

SOIC

M

Tube

CD74AC20M

AC20M

55 C to 125 C

SOIC – M

Tape and reel

CD74AC20M96

AC20M

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

C

D

OUTPUT

Y

H

H

H

H

L

L

XX

X

H

X

LX

X

H

X

XL

X

H

X

X

X

L

H

logic diagram (positive logic)

1A

1Y

1B

1C

1D

2A

2Y

2B

2C

2D

1

2

4

5

9

10

12

13

68

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

NC

1C

1D

1Y

GND

2D

2C

NC

2B

2A

2Y

E OR M PACKAGE

(TOP VIEW)

Copyright

 2002, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.