74LVC2G14 datasheet(2/17 Pages) PHILIPS

2 / 17 page

2004 Sep 08

Philips Semiconductors

Product speciﬁcation

Dual inverting Schmitt-trigger with

5 V tolerant input

74LVC2G14

FEATURES

• Wide supply voltage range from 1.65 V to 5.5 V

• 5 V tolerant input/output for interfacing with 5 V logic

• High noise immunity

• Complies with JEDEC standard:

– JESD8-7 (1.65 V to 1.95 V)

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V).

•±24 mA output drive (VCC = 3.0 V)

• CMOS low power consumption

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Mulltiple package options

• ESD protection:

– HBM EIA/JESD22-A114-B exceeds 2000 V

– MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 °C to +85 °C and

−40 °C to +125 °C.

APPLICATIONS

• Wave and pulse shapers for highly noisy environments

• Astable multivibrators

• Monostable multivibrators.

DESCRIPTION

The 74LVC2G14 is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. This

feature allows the use of this device as translator in a

mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down

applications using Ioff. The Ioff circuitry disables the output,

preventing the damaging backflow current through the

device when it is powered down.

The 74LVC2G14A provides two inverting buffers with

Schmitt-trigger action. It is capable of transforming slowly

changing input signals into sharply defined, jitter-free

output signals.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total switching outputs;

∑(CL × VCC2 × fo) = sum of outputs.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

propagation delay input nA to output nY

VCC = 1.8 V; CL = 30 pF; RL =1kΩ

5.6

VCC = 2.5 V; CL = 30 pF; RL = 500 Ω

3.7

VCC = 2.7 V; CL = 50 pF; RL = 500 Ω

4.1

VCC = 3.3 V; CL = 50 pF; RL = 500 Ω

3.9

VCC = 5.0 V; CL = 50 pF; RL = 500 Ω

2.7

input capacitance

3.5

CPD

power dissipation capacitance per buffer

VCC = 3.3 V; notes 1 and 2

18.1

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