AMC7836IPAPR datasheet(52/88 Pages) TI1

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AMC7836

SLAS986C – NOVEMBER 2014 – REVISED APRIL 2016

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7.6.4 General Device Configuration: Address 0x10 through 0x17

7.6.4.1 ADC Configuration Register (address = 0x10) [reset = 0x00]

Figure 74. ADC Configuration Register (R/W)

CMODE

CONV-RATE[1:0]

ADC-REF-

BUFF

Reserved

R/W-0

R/W-00

R/W-0

R/W-All zeros

Table 19. ADC Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

CMODE

R/W

ADC Conversion Mode Bit. This bit selects the ADC conversion

mode.

0: Direct mode. The analog inputs specified in the ADC

channel registers are converted sequentially one time.

When one set of conversions is complete, the ADC is idle

and waits for a new trigger.

1: Auto mode. The analog inputs specified in the AMC

channel

registers

are

converted

sequentially

and

repeatedly. When one set of conversions is complete, the

ADC multiplexer returns to the first channel and repeats the

process. The ADC-UPDATE bit in register 0x0F must be

used to initiate the transfer of the latest conversion data to

the ADC Data registers.

6-5

CONV-RATE[1:0]

R/W

ADC Conversion rate. See Table 20 to configure this setting.

ADC-REF-BUFF

R/W

ADC Reference Buffer bit. This bit must be set to 1 after device

power-up to enable the internal reference buffer driving the

ADC.

0: ADC reference buffer is disabled.

1: ADC reference buffer is enabled.

3-0

Reserved

R/W

All zeros

Reserved for factory use

Table 20. CONV-RATE[1:0] Bit Configuration

CONV-RATE[1:0]

Unipolar Channel Sample Time (µs)

Bipolar Channel Sample

Time (µs)

11.5

34.5

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