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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AMC7836IPAP bảng dữ liệu(PDF) 68 Page - Texas Instruments |
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AMC7836IPAP bảng dữ liệu(HTML) 68 Page - Texas Instruments |
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68 / 88 page  68 AMC7836 SLAS986C – NOVEMBER 2014 – REVISED APRIL 2016 www.ti.com Product Folder Links: AMC7836 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated 7.6.13.2 DAC Clear 1 Register (address = 0xB1) [reset = 0x00] Figure 109. DAC Clear 1 Register (R/W) 7 6 5 4 3 2 1 0 CLR-D15 CLR-D14 CLR-D13 CLR-D12 CLR-C11 CLR-C10 CLR-C9 CLR-C8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 58. DAC Clear 1 Register Field Descriptions Bit Field Type Reset Description 7 CLR-D15 R/W 0 This register uses software to force the DAC into a clear state. If CLRn = 1, DAC_n is forced into a clear state. If CLRn = 0, DAC_n is restored to normal operation. 6 CLR-D14 R/W 0 5 CLR-D13 R/W 0 4 CLR-D12 R/W 0 3 CLR-C11 R/W 0 2 CLR-C10 R/W 0 1 CLR-C9 R/W 0 0 CLR-C8 R/W 0 7.6.13.3 Power-Down 0 Register (address = 0xB2) [reset = 0x00] Figure 110. Power-Down 0 Register (R/W) 7 6 5 4 3 2 1 0 PDAC-B7 PDAC-B6 PDAC-B5 PDAC-B4 PDAC-A3 PDAC-A2 PDAC-A1 PDAC-A0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 59. Power-Down 0 Register Field Descriptions Bit Field Type Reset Description 7 PDAC-B7 R/W 0 After power-on or reset, all bits in the power-down register are cleared to 0, and all the components controlled by this register are either powered-down or off. The power-down register allows the host to manage the AMC7836 power dissipation. When not required, any of the DACs can be put into clamp mode and the ADC and internal reference into an inactive low-power mode to reduce current drain from the supply. The bits in the power-down register control this power-down function. Set the respective bit to 1 to activate the corresponding function. 6 PDAC-B6 R/W 0 5 PDAC-B5 R/W 0 4 PDAC-B4 R/W 0 3 PDAC-A3 R/W 0 2 PDAC-A2 R/W 0 1 PDAC-A1 R/W 0 0 PDAC-A0 R/W 0 |
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