AM1705DPTPD4 datasheet(93/165 Pages) TI1

93 / 165 page

AM1705

www.ti.com

SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014

Table 6-45. McASP0 Switching Characteristics(1)

No.

PARAMETER

MIN

MAX

UNIT

Cycle time, AHCLKR0 internal, AHCLKR0 output

Cycle time, AHCLKR0 external, AHCLKR0 output

tc(AHCLKRX)

Cycle time, AHCLKX0 internal, AHCLKX0 output

Cycle time, AHCLKX0 external, AHCLKX0 output

Pulse duration, AHCLKR0 internal, AHCLKR0 output

(AHR/2) – 2.5(2)

Pulse duration, AHCLKR0 external, AHCLKR0 output

(AHR/2) – 2.5(2)

tw(AHCLKRX)

Pulse duration, AHCLKX0 internal, AHCLKX0 output

(AHX/2) – 2.5(3)

Pulse duration, AHCLKX0 external, AHCLKX0 output

(AHX/2) – 2.5(3)

Cycle time, ACLKR0 internal, ACLKR0 output

greater of 2P or 25 ns(4)

Cycle time, ACLKR0 external, ACLKR0 output

greater of 2P or 25 ns(4)

tc(ACLKRX)

Cycle time, ACLKX0 internal, ACLKX0 output

greater of 2P or 25 ns(4)

Cycle time, ACLKX0 external, ACLKX0 output

greater of 2P or 25 ns(4)

Pulse duration, ACLKR0 internal, ACLKR0 output

(AR/2) – 2.5(5)

Pulse duration, ACLKR0 external, ACLKR0 output

(AR/2) – 2.5(5)

tw(ACLKRX)

Pulse duration, ACLKX0 internal, ACLKX0 output

(AX/2) – 2.5(6)

Pulse duration, ACLKX0 external, ACLKX0 output

(AX/2) – 2.5(6)

Delay time, ACLKR0 internal, AFSR output(7)

5.8

Delay time, ACLKX0 internal, AFSX output

5.8

Delay time, ACLKR0 external input, AFSR output (7)

2.5

11.6

td(ACLKRX-AFSRX)

Delay time, ACLKX0 external input, AFSX output

2.5

11.6

Delay time, ACLKR0 external output, AFSR output (7)

2.5

11.6

Delay time, ACLKX0 external output, AFSX output

2.5

11.6

Delay time, ACLKX0 internal, AXR0[n] output

5.8

td(ACLKX-AXRV)

Delay time, ACLKX0 external input, AXR0[n] output

2.5

11.6

Delay time, ACLKX0 external output, AXR0[n] output

2.5

11.6

Disable time, ACLKX0 internal, AXR0[n] output

5.8

tdis(ACLKX-AXRHZ)

Disable time, ACLKX0 external input, AXR0[n] output

11.6

Disable time, ACLKX0 external output, AXR0[n] output

11.6

(1)

McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1

ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

AHR - Cycle time, AHCLKR0.

(3)

AHX - Cycle time, AHCLKX0.

(4)

P = SYSCLK2 period

(5)

AR - ACLKR0 period.

(6)

AX - ACLKX0 period.

(7)

McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Links: AM1705

AM1705DPTPD4 bảng dữ liệu(PDF) 93 Page - Texas Instruments

AM1705DPTPD4 bảng dữ liệu(HTML) 93 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL