DP83223 datasheet(11/14 Pages) NSC

11 / 14 page

4.0 DC and AC Specifications (Continued)

Figure 4-2. Post Equalized Signal Detect Voltage

Figure 4-3.

Typical Schematic for 100BASE-TX signalling over Cat-5 UTP 100

Ω cable

Active PMID

Inactive PMID

SDTHoff

SDTHon

Post Equalized Signal Detect Voltage

DP83223

TXO+

TXGND

TXO-

GND

TXREF

RXI-

RXI+

SD+

SD-

ENCSEL

PMRD+

PMRD-

RXGND

EQSEL

LBEN

PMID+

PMID-

RREF

RJ-45

CDET

EXTVCC

VCC

TXVCC

RXVCC

VCC

Contact National Semiconductor

for further information relating to

available magnetics modules

VCC

GND

Data from

PHY

Device

SD To PHY

Device

Data to PHY or

Clock Recovery

The PMRD, SD and PMID 100K ECL differential signal must be

terminated into a standard ECL load of 50

Ω to VCC-2.0V or equivalent:

i.e. Thevenin of 130

Ω to GND accompanied by 82Ω to VCC

= Murata # BLM31A02PT (1206 package)

*510

Ω

Transmit

Magnetics

Receive

Magnetics

float

37.9

Ω

All resistors are 1/10th Wt, 1% tolerance

Device

37.9

Ω

12.1

Ω 12.1Ω

0.01uF

Ω

0.01uF

The Receive Attenuation / Termination network

must be optimized to compensate for the insertion

loss of the receive magnetics.

Please refer to the National Semiconductor Application Note

entitled “DP83223 Adaptive Equalization Considerations”

for further detail. The values provided in this example

are targeted to match an insertion loss of approximately

0.4dB (approximately 90mV pk-pk differential of loss for

a typical scrambled IDLE line state) which will result in

All capacitors are 16V ceramic

Common Mode Noise Filter

*The Rref resistor value may need to be adjusted

to compensate for transmit magnetics insertion

loss in order to achieve the standard specific

2.0V pk-pk differential TXO+/- output amplitude

as measured across the RJ45 transmit pins.

a final amplitude of approximately 1.45V pk-pk differential

as seen across the RXI+/- inputs for zero Meters of cable.

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