ADC10321 datasheet(21/26 Pages) TI1

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ADC10321

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SNAS028F – JUNE 2000 – REVISED MAY 2013

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers has to

charge for each conversion, the more instantaneous digital current is required from VD and DGND. These large

charging current spikes can couple into the analog section, degrading dynamic performance. Adequate

bypassing and maintaining separate analog and digital ground planes will reduce this problem on the board.

Buffering the digital data outputs (with an 74F541, for example) may be necessary if the data bus to be driven is

heavily loaded. Dynamic performance can also be improved by adding series resistors of 47

Ω at each digital

output.

Driving the VREF+ F pin or the VREF− F pin with devices that can not source or sink the current required

by the ladder. As mentioned in REFERENCE INPUTS, be careful to see that any driving devices can source

sufficient current into the VREF+ F pin and sink sufficient current from the VREF− F pin. If these pins are not driven

with devices than can handle the required current, they will not be held stable and the converter output will

exhibit excessive noise.

Using a clock source with excessive jitter. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate.

Using the same voltage source for VD and other digital logic. As mentioned in POWER SUPPLY

CONSIDERATIONS, VD should use the same power source used by VA, but should be decoupled from VA.

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