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ADC12DL040CIVS/NOPB bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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ADC12DL040CIVS/NOPB bảng dữ liệu(HTML) 1 Page - Texas Instruments |
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1 / 37 page ![]() ADC12DL040 www.ti.com SNAS250D – FEBRUARY 2005 – REVISED APRIL 2013 ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter Check for Samples: ADC12DL040 1 FEATURES DESCRIPTION The ADC12DL040 is a dual, low power monolithic 23 • Single +3.0V Supply Operation CMOS analog-to-digital converter capable of • Internal Sample-and-Hold converting analog input signals into 12-bit digital • Internal Reference words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with • Outputs 2.4V to 3.6V Compatible digital error correction and an on-chip sample-and- • Power Down Mode hold circuit to minimize power consumption while • Duty Cycle Stabilizer providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single • Multiplexed Output Mode +3.0V power supply, the ADC12DL040 achieves 11.1 effective bits at nyquist and consumes just 210 mW APPLICATIONS at 40 MSPS, including the reference current. The • Ultrasound and Imaging Power Down feature reduces power consumption to 36 mW. • Instrumentation • Communications Receivers The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility • Sonar/Radar of a single-ended input. Full use of the differential • xDSL input is recommended for optimum performance. The • Cable Modems digital outputs from the two ADC's are available on a single multiplexed 12-bit bus or on separate buses. • DSP Front Ends Duty cycle stabilization and output data format are selectable using a quad state function pin. The output KEY SPECIFICATIONS data can be set for offset binary or two's complement. • Resolution 12 Bits To ease interfacing to lower voltage systems, the • DNL ±0.3 LSB (typ) digital output driver power pins of the ADC12DL040 • SNR (fIN = 10 MHz) 69 dB (typ) can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. • SFDR (fIN = 10 MHz) 85 dB (typ) • Data Latency 7 Clock Cycles This device is available in the 64-lead TQFP package and will operate over the industrial temperature range • Power Consumption of −40°C to +85°C. An evaluation board is available – Operating 210 mW (typ) to ease the evaluation process. – Power Down Mode 36 mW (typ) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 TRI-STATE is a registered trademark of National Semiconductor Corporation. 3 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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